PRINCIPAL PCIE LOGIC DESIGN

Semiconductor Engineering; Hillsboro (OR); On-site; USD 140,000 - 200,000; Full time

Job summary

Rambus in Hillsboro, Oregon, is seeking a motivated Principal Design Engineer to join our PCIe IP design team. This full-time role focuses on architecture and design of next-generation PCIe IPs and prototyping these IPs on cutting-edge FPGAs.

You will collaborate with local teams and international colleagues to push the boundaries of data speed and safety, contributing to innovative silicon IP solutions across multiple projects.

Job description

Rambus, a premier chip and silicon IP provider, is seeking to hire a motivated full-time Principal Design engineer to join our PCIe IP design team. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer.

This full-time position will allow the candidate to contribute to the architecture, design of next generation IPs, targeting the latest developments in PCIe standards. This position will also be involved in prototyping these IPs on cutting edge FPGAs. The candidate will work closely with local teams as well as with multi-cultural, multi-national colleagues.