Senior Hardware Design Engineer: RTL/ASIC & FPGA

Rambus; Hillsboro (OR); On-site; USD 100,000 - 130,000; Full time

Job summary

Rambus is seeking a qualified candidate for a role in Hillsboro, Oregon, emphasizing strong expertise in System Verilog/Verilog RTL design. Responsibilities include RTL coding, integration, and customer support. The ideal candidate will have substantial experience in ASIC or FPGA design, strong communication skills, and a Bachelor's in Electrical Engineering (BSEE). Expertise in simulation tools and ability to work independently are preferred. Join our innovative team to contribute to cutting-edge memory solutions.

Qualifications

• 5+ years of logic design experience is required.
• Strong communication and project management skills are essential.
• Willingness to learn quickly and work independently.

Responsibilities

• Design architecting and trade-off analysis.
• Perform RTL coding and verification.
• Integrate and verify Memory Controller + PHY.

Skills

System Verilog/Verilog RTL design expertise

Questa/Incisive/VCS simulator experience

Python/Perl/Tcl scripting experience

ASIC/FPGA design experience

Solid communication skills

Project management skills

Logic design experience

Education

BSEE

Job description

Rambus is seeking a qualified candidate for a role in Hillsboro, Oregon, emphasizing strong expertise in System Verilog/Verilog RTL design. Responsibilities include RTL coding, integration, and customer support. The ideal candidate will have substantial experience in ASIC or FPGA design, strong communication skills, and a Bachelor's in Electrical Engineering (BSEE). Expertise in simulation tools and ability to work independently are preferred. Join our innovative team to contribute to cutting-edge memory solutions.