Principal NAND Datapath Architect | AI-Driven Design Leader

Micron Technology, Inc.; San Jose (CA); On-site; USD 181,000 - 308,000; Full time

Job summary

Micron Technology, Inc. in California is seeking a Principal Design Engineer to lead the architecture and design of the NAND datapath between the page buffer and IO, including wave-pipelined buses, FIFOs, dataline sensing and clocking.

You will apply AI daily to accelerate timing closure, verify designs, and help advance semi-custom methodology from SPICE-only closure to model-based flows. The role requires collaboration with layout, test, and firmware teams and hands-on leadership.

Qualifications

• BS/MS in EE or related field with 8+ years in memory datapath.
• Deep expertise in flop-to-flop and wave-pipelined timing closure.
• Experience in sense amp, dataline or SRAM read/write design.
• Daily hands-on AI use with concrete examples of improved design productivity.

Responsibilities

• Define, design and verify internal datapath blocks (page buffer-to-IO data buses, wave pipelines, FIFOs, SER/DES fronts) to meet bandwidth, timing and power targets.
• Architect and close wave-pipelined and flop-to-flop paths, including setup/hold, skew, and PVT margins.
• Design dataline sense amps and precharge/latch sensing with margin analyses.
• Lead semi-custom methodology and AI-driven timing/verification workflows.
• Collaborate with layout, test, and firmware teams; mentor engineers.

Skills

AI-driven design workflows

Wave-pipelined timing

Datapath architecture

RTL scripting

Layout collaboration

Education

BS/MS in EE or related field

Tools

SPICE

ECO tooling

Job description

Micron Technology, Inc. in California is seeking a Principal Design Engineer to lead the architecture and design of the NAND datapath between the page buffer and IO, including wave-pipelined buses, FIFOs, dataline sensing and clocking.

You will apply AI daily to accelerate timing closure, verify designs, and help advance semi-custom methodology from SPICE-only closure to model-based flows. The role requires collaboration with layout, test, and firmware teams and hands-on leadership.