Principal IO Design Engineer — AI-Driven NAND

Micron Technology, Inc.; San Jose (CA); Hybrid; USD 181,000 - 361,000; Full time

Benefits offered by this job

Medical, dental and vision plans

Paid time off and holidays

Bonuses and equity

Job summary

Micron Technology in San Jose, CA, seeks a Principal Design Engineer to own the IO architecture for high-speed NAND interfaces, guiding design from architecture to silicon. The role emphasizes AI-driven workflow improvements and cross-functional collaboration with design and applications teams.

You will lead timing budgets, oversee verification across channels and power delivery, and drive efficiency through AI-enabled techniques. A strong background in IO and mixed-signal design is required.

Qualifications

• 12+ years of high-speed IO or mixed-signal IC design, including leading IO architecture on multiple products
• Expertise in high-speed transmitter and receiver design and IO timing analysis
• Experience closing IO timing across PVT, mismatch and aging; strong physical design teamwork

Responsibilities

• Define, design and verify major IO blocks to meet ONFI/JEDEC timing and electrical specs
• Lead the IO timing budget and coordinate channel, package and power-delivery effects with SI/PI
• Optimize IO power and area; drive floorplanning, pad-ring and layout guidance
• Mentor engineers, present at design reviews, and build AI-enabled workflows

Skills

High-speed IO design

Mixed-signal IC design

AI tools in engineering

Leadership & mentorship

Education

BS/MS/PhD in Electrical Engineering

Tools

IBIS/S-parameter models

Post-layout verification tools

Job description

Micron Technology in San Jose, CA, seeks a Principal Design Engineer to own the IO architecture for high-speed NAND interfaces, guiding design from architecture to silicon. The role emphasizes AI-driven workflow improvements and cross-functional collaboration with design and applications teams.

You will lead timing budgets, oversee verification across channels and power delivery, and drive efficiency through AI-enabled techniques. A strong background in IO and mixed-signal design is required.