AI-Optimized Memory Architect for SoC RTL

Micron Technology, Inc; Folsom (CA); On-site; USD 175,000 - 309,000; Full time

Job summary

Micron Technology, Inc. is hiring for a Member of Technical Staff to translate architectural vision into silicon-proven hardware. You will design SystemVerilog RTL for memory system architectures and optimize area, power, and timing through synthesis and PPA analysis.

The role requires a strong background in digital design, memory systems, and programming in C/C++, Python, or similar. Bachelor's degree in CS/CE/EE is required; advanced degrees are a plus.

Qualifications

• Bachelor’s degree in Computer Science, Computer Engineering, Electrical Engineering, or a related technical field.
• Strong experience in digital design and microarchitecture development with ownership of hardware blocks from specification through implementation.
• Solid understanding of computer architecture and memory systems, including SoC-level behaviors and tradeoffs.
• Experience with synthesis flows and early PPA estimation and optimization.
• Proficiency in SystemVerilog and at least one programming language such as C, C++, or Python.

Responsibilities

• Translate architecture requirements into scalable microarchitectures and drive implementation from concept through silicon.
• Design, implement, and review SystemVerilog RTL for advanced memory system architectures.
• Perform synthesis and early PPA analysis to optimize area, power, and timing.
• Develop and maintain microarchitecture documentation that aligns design intent across teams.
• Evaluate architectural and implementation tradeoffs to support technical decision-making.

Skills

SystemVerilog

Digital design

Microarchitecture

C/C++/Python

Education

Bachelor's degree in CS/CE/EE

Tools

Synthesis tools

PPA analysis tools

Job description

Micron Technology, Inc. is hiring for a Member of Technical Staff to translate architectural vision into silicon-proven hardware. You will design SystemVerilog RTL for memory system architectures and optimize area, power, and timing through synthesis and PPA analysis.

The role requires a strong background in digital design, memory systems, and programming in C/C++, Python, or similar. Bachelor's degree in CS/CE/EE is required; advanced degrees are a plus.