Senior Custom Memory Design Engineer: SRAMs & Registers

Nuvacore; Austin (TX); Presencial; USD 140 000 - 200 000; Tempo integral

Resumo da oferta

Nuvacore is building ground-up high performance, low-power CPUs for next-generation compute workloads. As a Custom Memory Design Engineer, you will own schematic development for SRAMs and register files, and drive PDV closure across advanced CMOS nodes.

You will partner with Foundry/PDK, CAD and RTL/DFT teams to optimize memory IP, define memory specifications for RTL, and push automation to raise design efficiency. A strong track record in tape-out is essential.

Qualificações

• 8+ years of experience in custom memory circuit design (SRAMs, register files).
• Hands-on transistor-level circuit design with memory arrays, decoders, sense amps.
• Proficiency in SPICE, memory margins, and memory cell architectures.
• Proficient with industry-standard EDA tools for schematic, layout, extraction and characterization.
• Track record delivering production-level custom memory IP through tape-out with silicon-validated PPA.

Responsabilidades

• Own schematic development and characterize custom memories (SRAM, register files).
• Supervise layout implementation and PDV closure, driving physical verification.
• Own end-to-end memory sign-off across DRC/LVS/antenna, extraction, timing and power.
• Collaborate with foundry/PDK, CAD, RTL and DFT teams to benchmark new process tech.
• Collaborate with RTL, providing explicit custom memory specs and timing behavior.
• Drive Tools/Flows/Methodology (TFM) to raise design efficiency and best practices.

Conhecimentos

8+ years custom memory design

SPICE simulations

End-to-end memory sign-off

Python/Perl/TCL scripting

Communication and collaboration

Tape-out silicon validation

Formação académica

BS or MS in Electrical Engineering or related field

Ferramentas

Cadence tools

Descrição da oferta de emprego

Nuvacore is building ground-up high performance, low-power CPUs for next-generation compute workloads. As a Custom Memory Design Engineer, you will own schematic development for SRAMs and register files, and drive PDV closure across advanced CMOS nodes.

You will partner with Foundry/PDK, CAD and RTL/DFT teams to optimize memory IP, define memory specifications for RTL, and push automation to raise design efficiency. A strong track record in tape-out is essential.