Principal Front-End Design Engineer

Synopsys, Inc.; Sunnyvale (CA); Sur place; USD 180 000 - 240 000; Plein temps

Résumé du poste

Synopsys, Inc. seeks a Principal Front-End Design Engineer in Sunnyvale, CA to lead methodology, subsystem architecture, and AI-enabled design innovation across IP and SoC development.

You will build scalable design solutions, improve engineering productivity, and drive best practices across global teams. The role includes developing AI-driven verification and synthesis flows, architecting reusable subsystem reference designs, and mentoring engineers.

Qualifications

• Relevant degree and extensive hands-on ASIC/SoC/IP experience.
• Proven leadership across cross-functional engineering teams.
• Expertise in verification, synthesis, timing constraints, DFT, CDC/RDC, or lint methodologies.

Responsabilités

• Develop and deploy AI-driven solutions for verification, synthesis, constraints, and DFT workflows.
• Architect reusable subsystem reference designs for Synopsys IP.
• Debug and optimize front-end design methodologies and automation flows.
• Drive adoption of best practices across design and verification teams.
• Collaborate with EDA, IP, and customer-facing engineers to solve design challenges.
• Mentor engineers through technical leadership and knowledge sharing.

Connaissances

Technical leadership

Cross-functional collaboration

Mentoring

SystemVerilog/UVM

Python

Strong problem-solving

Communication skills

Formation

10+ years ASIC/SoC/IP design and verification experience

BS/MS in Electrical Engineering or Computer Engineering

Outils

VCS

VC SpyGlass

Fusion Compiler

Design Compiler

TestMAX

Description du poste

We Are

Synopsys is a leader in silicon-to-systems engineering solutions, helping customers accelerate innovation in AI-driven products through industry-leading EDA, IP, and design solutions.

You Are

As a Principal Front-End Design Engineer, you will lead methodology, subsystem architecture, and AI-enabled design innovation across IP and SoC development. You will build scalable design solutions, improve engineering productivity, and drive best practices across global teams.

What You'll Be Doing

• Develop and deploy AI-driven solutions for verification, synthesis, constraints, and DFT workflows.
• Architect reusable subsystem reference designs for Synopsys IP.
• Debug and optimize front-end design methodologies and automation flows.
• Drive adoption of best practices across design and verification teams.
• Collaborate with EDA, IP, and customer-facing engineers to solve complex design challenges.
• Mentor engineers through technical leadership and knowledge sharing.

What You'll Need

• BS/MS in Electrical Engineering, Computer Engineering, or related field.
• 10+ years of ASIC, SoC, or IP design and verification experience.
• Expertise in verification, synthesis, timing constraints, DFT, CDC/RDC, or lint methodologies.
• Strong experience with Synopsys tools such as VCS, VC SpyGlass, Fusion Compiler, Design Compiler, and TestMAX.
• Proficient in SystemVerilog, UVM, Tcl, Python, or similar languages.
• Demonstrated technical leadership and influence across cross-functional engineering teams.

What Sets You Apart

• Deep understanding of IP reuse, subsystem integration, and SoC development.
• Passion for applying AI to improve design productivity and quality.
• Strong problem-solving, communication, and mentoring skills.
• Ability to translate complex technical challenges into scalable, practical solutions.

The Team You'll Be Part Of

You will be a member of the Digital Methodology Interop Engineering team, a team of engineers dedicated to advancing IP and subsystem design excellence at Synopsys. The team collaborates across global sites, driving innovation in methodology, tool integration, and best practices. You will help shape the future of SoC design with Synopsys IP.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.