Design Engineering Director

CADENCE US; Austin (TX); On-site; USD 140,000 - 210,000; Full time

Job summary

Cadence Design Systems, Inc. in Austin, TX seeks an experienced Front End Design engineer to lead RTL design projects. You will mentor a team of RTL design engineers and drive microarchitectural features for IPs and subsystems, ensuring PPA goals are met.

The role requires hands-on RTL development in Verilog/SystemVerilog/VHDL and oversight of pre-silicon verification, including Lint, CDC, FV, and quality checks, with collaboration across DV, PD, architecture, and firmware teams.

Qualifications

• 10+ years of Front End design and/or verification in semiconductor industry.
• Experience in leading and managing complex engineering projects.
• Rich experience in IP creation and/or SoC and IP integration.
• Expert in RTL design (Verilog), simulators/debuggers.
• Hands on experience in Synthesis, SDC creation and support PD and STA teams.

Responsibilities

• Technical Leadership: Guide and mentor a team of RTL design engineers.
• Design & Microarchitecture: Define and develop microarchitectural features for IPs and subsystems.
• RTL Development: Write, debug, and optimize RTL code in Verilog, SystemVerilog, or VHDL.

Skills

Front End design

RTL design

Leadership

SoC/IP integration

Verilog/SystemVerilog/VHDL

Synthesis/PD/STA

Education

BS/MS Engineering or Computer Sciences

Tools

Cadence Front End Toolset

Simulators

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence Solutions (North America) team is looking for an experienced candidate to lead Front End Design projects. This is a challenging and rewarding opportunity is for a highly motivated engineer with a passion for innovation and a proven track record of success in the semiconductor industry.

Responsibilities

• Technical Leadership: Guide and mentor a team of RTL design engineers, fostering a collaborative and innovative environment.
• Design & Microarchitecture: Define and develop microarchitectural features for IPs and subsystems, ensuring they meet PPA goals.
• RTL Development: Write, debug, and optimize RTL code in Verilog, SystemVerilog, or VHDL to create complex digital logic.
• Verification & Signoff: Oversee pre-silicon verification activities, including Lint, Clock Domain Crossing (CDC), Formal Verification (FV), and other quality checks.
• Collaboration: Work closely with cross-functional teams, including Design Verification (DV), Physical Design (PD), Architecture, and firmware engineers, to ensure successful delivery.

Qualifications

• *10+ years of Front End design and/or verification with a BS/MS Engineering or Computer Sciences
• *Proven experience in leading and managing complex engineering projects
• *Rich experience in IP creation and/or SoC and IP (CPU, Memory, Interface) integration
• *Expert in RTL design (Verilog), simulators debuggers
• *Hands on Experience in Synthesis, SDC creation and support PD and STA teams.
• *Experience in driving results in multi-disciplinary organization

Desirable

A Self-motivated person with good communication and design management skills Experience with Cadence front end toolset. We’re doing work that matters.

We’re doing work that matters. Help us solve what others can’t. We’re doing work that matters. Help us solve what others can’t.

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Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences.

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