Principal DV Engineer: SerDes/PHY IP for AI Systems

Astera Labs; San Jose (CA); Hybrid; USD 207,000 - 230,000; Full time

Job summary

Astera Labs is seeking a Principal Design Verification Engineer to own functional verification of high-speed SerDes/PHY IP. You will architect verification environments, drive coverage closure, and ensure first-pass silicon success across PCIe Gen 6/7, UALink, UCIe, and Ethernet interfaces.

You will collaborate with analog/mixed-signal designers, digital architects, and SoC teams to verify multi-Gbps SerDes blocks and guide the DV team through tape-out readiness and post-silicon validation.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related field.
• 8+ years of design verification experience on high-speed SerDes, PHY, or mixed-signal IP.
• Strong understanding of the physical layer, including CTLE, DFE, FFE, CDR, training sequences, and link bring-up.
• Expert-level proficiency in SystemVerilog and UVM.
• Hands-on experience with analog/mixed-signal co-simulation and Real Number Modeling (RNM).
• Working knowledge of high-speed serial protocols: PCIe, UALink, UCIe, Ethernet, or CXL.

Responsibilities

• Architect UVM-based verification environments for SerDes/PHY IP, including PMA, PCS, and PHY-MAC interface layers.
• Define verification plans, coverage models, and sign-off criteria for high-speed serial link blocks.
• Drive methodology decisions across analog/mixed-signal co-simulation, gate-level simulation, and emulation flows.

Skills

SystemVerilog

UVM

SerDes verification

RNM

AMS co-simulation

High-speed protocols

Education

Bachelor's degree in EE/CE

Tools

Palladium

Veloce

ZeBu

Job description

Astera Labs is seeking a Principal Design Verification Engineer to own functional verification of high-speed SerDes/PHY IP. You will architect verification environments, drive coverage closure, and ensure first-pass silicon success across PCIe Gen 6/7, UALink, UCIe, and Ethernet interfaces.

You will collaborate with analog/mixed-signal designers, digital architects, and SoC teams to verify multi-Gbps SerDes blocks and guide the DV team through tape-out readiness and post-silicon validation.