Interface IP Design Verification Engineer (PCIe/Ethernet)

The Consensus; San Jose (CA); On-site; USD 140,000 - 190,000; Full time

Benefits offered by this job

Medical insurance

Dental insurance

Vision insurance

Housing subsidy

Relocation support

Wellness programs

Daily lunch

Unlimited compute budget

Job summary

Etched is seeking a Design Verification Engineer for the Interface IP DV team. You will validate the architecture requirements across IP subsystems and interfaces, ensuring correctness and performance from hardware to software.

The role demands creativity and deep technical ability to tackle challenging verification tasks. You will own end-to-end verification for IP subsystems, work with vendor IP configurations, and develop scalable testbenches using SystemVerilog/UVM.

Qualifications

• 5+ years of design verification experience.
• Creativity to surface corner-case bugs in complex hardware.
• Hands-on with SystemVerilog/UVM verification methodologies.
• Experience with standard IP interfaces and protocols (PCIe, Ethernet, AXI/AMBA, ARM/ARC CPUs).
• Ability to own projects in a fast-paced startup environment and collaborate cross-functionally.

Responsibilities

• Own end-to-end verification for one or more IP subsystems (PCIe, Ethernet, CPU, peripherals).
• Understand vendor IP configurations and coordinate with internal IP teams.
• Develop and maintain UVM/SystemVerilog-based verification environments for correctness and performance.
• Collaborate with integration and SoC DV teams to validate IP interactions.
• Drive coverage closure and sign-off by identifying gaps and corner cases.

Skills

SystemVerilog/UVM

IP/SoC verification

Testbench development

Debug complex bugs

Tools

UVM

Job description

Etched is seeking a Design Verification Engineer for the Interface IP DV team. You will validate the architecture requirements across IP subsystems and interfaces, ensuring correctness and performance from hardware to software.

The role demands creativity and deep technical ability to tackle challenging verification tasks. You will own end-to-end verification for IP subsystems, work with vendor IP configurations, and develop scalable testbenches using SystemVerilog/UVM.