Interface IP DV Engineer (PCIe/Ethernet)

The Consensus; Austin (TX); Hybrid; USD 130,000 - 170,000; Full time

Benefits offered by this job

Health benefits

$500 monthly waiver credit

Wellness programs

Daily meals in office

Compute budget

Job summary

Etched is seeking a Design Verification Engineer to join the Interface IP DV team in Austin, with hybrid collaboration across San Jose. You will verify IP subsystems, ensure correctness across the hardware-software stack, and tackle challenging verification tasks in a fast-paced startup setting.

You will own verification of multiple IP subsystems, develop scalable testbenches, and collaborate with RTL, software, and emulation teams to ensure robust integration and performance across the chip

Qualifications

• 5+ years of design verification experience.
• Strong ability to tackle complex verification challenges and expose corner-case bugs.
• Hands-on experience with SystemVerilog/UVM and building scalable, reusable testbenches.
• Familiarity with IP interfaces and protocols like PCIe, Ethernet, AXI/AMBA, or ARM/ARC CPUs.

Responsibilities

• End-to-end ownership of IP subsystems (PCIe, Ethernet, CPU, low power peripherals, sensors).
• Understand vendor IP configurations and handshake with internal IP team.
• Develop and maintain UVM/SystemVerilog verification environments for functional correctness and performance.
• Collaborate with integration and SoC DV teams to validate IP interactions within the chip architecture.
• Drive coverage closure and sign-off by defining metrics and analyzing gaps across corner cases.

Skills

SystemVerilog

UVM

IP verification

PCIe

Ethernet

AXI/AMBA

ARM/ARC CPUs

Collaboration

Job description

Etched is seeking a Design Verification Engineer to join the Interface IP DV team in Austin, with hybrid collaboration across San Jose. You will verify IP subsystems, ensure correctness across the hardware-software stack, and tackle challenging verification tasks in a fast-paced startup setting.

You will own verification of multiple IP subsystems, develop scalable testbenches, and collaborate with RTL, software, and emulation teams to ensure robust integration and performance across the chip