Distinguished Formal Verification Architect

Astera Labs; San Jose (CA); On-site; USD 260,000 - 380,000; Full time

Job summary

Astera Labs in San Jose, California seeks a Distinguished Engineer, Formal Verification to lead the strategy across PCIe Gen 6/7, CXL, Ethernet, UCIe and UALink. As a technical authority, you will define methodologies, improve design quality, and mentor a global team of engineers.

You will drive cross‑functional collaboration, develop test plans, implement formal models, and represent Astera Labs at industry forums.

Qualifications

• Proven expertise in formal verification methodologies and best practices.
• Strong background in SystemVerilog/Verilog and design verification.
• Experience leading and mentoring global engineering teams.

Responsibilities

• Define and evolve formal verification strategy across PCIe, CXL, Ethernet, UCIe, and UALink.
• Serve as technical authority on formal verification and risk mitigation.
• Mentor engineers across global sites and engage with industry forums.

Skills

SystemVerilog/Verilog

Python/Perl scripting

Strategic leadership

Mentoring

Cross-functional collaboration

Formal verification strategy

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science

Master's or PhD in Electrical/Computer Engineering or Computer Science

Tools

Synopsys VCFormal

Cadence JasperGold

Job description

Astera Labs in San Jose, California seeks a Distinguished Engineer, Formal Verification to lead the strategy across PCIe Gen 6/7, CXL, Ethernet, UCIe and UALink. As a technical authority, you will define methodologies, improve design quality, and mentor a global team of engineers.

You will drive cross‑functional collaboration, develop test plans, implement formal models, and represent Astera Labs at industry forums.