Principal Digital Verification Engineer

USA Tech Recruit; Town of Pittsford (NY); On-site; USD 170,000 - 210,000; Full time

Job summary

USA Tech Recruit is seeking a Principal Digital Verification Engineer in Rochester, NY to lead verification strategies for complex digital subsystems in optical networking products.

You will own verification methodologies, drive coverage, mentor engineers and act as ASIC Verification Prime when assigned, collaborating with design, systems, and architecture teams.

Qualifications

• 12+ years of hands-on experience in digital verification.
• Strong proficiency in SystemVerilog, UVM and SystemVerilog Assertions (SVA).
• Experience defining verification strategies, test planning and coverage.
• Experience with industry-standard digital simulation tools.

Responsibilities

• Define verification strategies and lead digital subsystem verification.
• Develop verification environments and test scenarios with functional coverage plans.
• Drive verification quality and identify gaps in coverage.
• Provide technical leadership and mentor engineers.

Skills

SystemVerilog

UVM

SVA

Education

Bachelor's degree or higher in Electrical Engineering, Computer Engineering, Computer Science or related field

Tools

Digital verification tools

Job description

A global technology company develops advanced optical networking and high-speed connectivity solutions that power modern telecommunications infrastructure and the growing demands of AI and cloud computing. Its products enable high-capacity data transmission across optical fibre networks, supporting the performance, reliability and scalability required by next-generation communications systems.

The company is seeking a Principal Digital Verification Engineer to lead and shape verification strategies for complex digital subsystems used in advanced optical transmission products. Based in Rochester, New York, you will work closely with digital design engineers, verification specialists, systems engineers and architects to ensure designs meet functional requirements and deliver the performance and reliability expected of high-speed networking technologies.

This is a senior technical role for an experienced verification engineer with deep expertise in SystemVerilog, UVM and assertion-based verification. You will own verification methodologies, drive coverage and test planning, troubleshoot complex design issues, and provide technical leadership across projects. There will also be opportunities to mentor colleagues and take responsibility for verification activities as the designated ASIC Verification Prime.

Key Responsibilities:

• Define verification strategies: Analyse system architectures and functional requirements, collaborating with systems engineers and architects to establish comprehensive digital verification approaches.
• Lead digital subsystem verification: Validate complex digital designs using simulation-based verification, functional coverage methodologies and, where appropriate, formal verification techniques.
• Develop verification environments: Create, review and optimise simulation environments, test scenarios, functional coverage plans and formal verification test plans.
• Drive verification quality and coverage: Identify gaps in verification coverage, improve test effectiveness and ensure verification activities align with architectural requirements and project objectives.
• Provide technical leadership: Lead focused technical initiatives, resolve complex verification challenges and mentor other engineers where required.
• Own verification delivery: Estimate project timelines, track progress against agreed plans, manage priorities and communicate status, risks and dependencies to relevant stakeholders.
• Lead ASIC verification activities: Take responsibility as the ASIC Verification Prime when assigned, coordinating verification execution and ensuring deliverables meet project requirements.
• Contribute to design and architecture reviews: Assess proposed architectures and digital designs for verification implications, identifying opportunities to improve coverage, technical quality and schedule execution.
• Debug complex technical issues: Work closely with design and engineering teams to investigate failures, determine root causes and support timely resolution.

Key Qualifications:

• Experience: 12+ years of hands-on experience in digital verification, with strong proficiency in SystemVerilog, UVM and SystemVerilog Assertions (SVA).
• Verification methodology: Demonstrated ability to define and implement comprehensive digital verification strategies, including test planning, simulation, functional coverage and verification closure.
• Simulation tools: Experience working with industry-standard digital simulation tools from major EDA vendors.
• Technical problem-solving: Strong debugging skills and a structured, methodical approach to resolving
• Technical leadership: Ability to work independently, take ownership of verification deliverables and collaborate effectively with multidisciplinary engineering teams. Experience mentoring engineers or leading verification initiatives is beneficial.
• Education: Bachelor's degree or higher in Electrical Engineering, Computer Engineering, Computer Science or a related scientific or engineering discipline.
• Communication: Strong written and verbal English communication skills, with the ability to communicate technical findings, project status and risks clearly.

Experience in the following areas would be advantageous:

• Formal verification: Practical experience applying formal verification techniques to digital designs.
• DSP and error correction: Familiarity with digital signal processing (DSP) and/or Forward Error Correction (FEC) technologies.
• Development workflows: Experience using Jira for issue tracking and Git for source control and revision management.
• Scripting and programming: Familiarity with Python, Make, Bash, object-oriented programming, C and C++.

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