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European Tech Recruit is seeking a Principal Digital Verification Engineer to spearhead digital verification strategies for ASIC and optical networking products. The role involves collaboration with systems engineers and architects to define verification plans, and leadership of verification initiatives across the project lifecycle.
The ideal candidate brings 12+ years of SystemVerilog/UVM/SVA experience, DSP know-how, and a track record of mentoring teams.
Principal Digital Verification Engineer – SystemVerilog / UVM / SVA / ASIC / Optical Networking
We are currently partnered with a telecommunications technology organisation developing advanced optical transmission and networking solutions. This opportunity focuses on digital verification for high-speed optical networking products, with responsibility for defining verification strategies, validating digital subsystems, optimising verification environments and collaborating with design engineers, systems engineers and architects.
Principal Digital Verification Engineer / Digital Verification / ASIC Verification / ASIC Verification Prime / SystemVerilog / UVM / Universal Verification Methodology / SVA / SystemVerilog Assertions / Digital Design Verification / Functional Verification / Verification Strategy / Functional Coverage / Coverage Planning / Simulation / Formal Verification / Verification Test Plans / Testbench Development / Simulation Environments / Test Scenario Development / Digital Subsystems / Architecture Reviews / Design Reviews / Technical Leadership / Mentoring / Debugging / Optical Networking / Optical Transmission / High-Speed Connectivity / Telecommunications / Digital Signal Processing / DSP / Forward Error Correction / FEC / Jira / Git / Python / Make / Bash / Object-Oriented Programming / OOP / C / C++ / Electrical Engineering / Computer Engineering / Computer Science / Rochester / New York
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