Principal Digital Design Engineer – SoC & IP Innovator

Microchip

Chandler, Northern (AZ, KY)

Hybrid

USD 75,000 - 232,000

Full time

14 days+
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Benefits offered by this job

Health benefits from day one
ESPP with 2-year look-back
Retirement savings plan

Job summary

Microchip Technology Inc. is seeking a Principal Digital Design Engineer to lead RTL development and SoC integration for mixed-signal microcontrollers. You will drive digitals from concept to tape-out, mentor teams, and collaborate with analog, architecture, and product groups.

The role requires 10+ years in ASIC/SoC design and verification, strong RTL skills, and experience with EDA flows. Hybrid/onsite options in the US support fast-paced silicon delivery.

Qualifications

  • B.S. in Electrical Engineering, Computer Engineering, or related field with 10+ years' experience in ASIC/SoC Digital Design and Verification.
  • Strong foundations in digital logic / finite state machine design, computer architecture, RTL coding, and SoC integration techniques.
  • Working knowledge of Physical Design / APR concepts and flows (synthesis, floorplanning, place-and-route, CTS, ECO).
  • Familiarity with industry EDA flows / tools (Cadence, Synopsys, Siemens), Linux, Windows.
  • Scripting skills (Python / Perl / Tcl) for productivity and flow automation.

Responsibilities

  • Own and drive digital block and subsystem design from concept through tape-out.
  • Develop high-quality RTL for digital peripherals and IP (8/32-bit blocks).
  • Lead block- and SoC-level verification and integration, including digital verification, UPF/low-power, AMS/mixed-signal collaboration, STA, and ECO support.

Skills

RTL design
Verilog/SystemVerilog
SoC integration
Digital verification
UPF & low-power
AMS/mixed-signal verification
STA
PD/Place & Route coordination
EDA tool flows
Python/Perl/Tcl

Education

B.S. in Electrical/Computer Engineering
M.S. preferred

Tools

Cadence
Synopsys
Siemens
Linux
Windows

Job description

Microchip Technology Inc. is seeking a Principal Digital Design Engineer to lead RTL development and SoC integration for mixed-signal microcontrollers. You will drive digitals from concept to tape-out, mentor teams, and collaborate with analog, architecture, and product groups.

The role requires 10+ years in ASIC/SoC design and verification, strong RTL skills, and experience with EDA flows. Hybrid/onsite options in the US support fast-paced silicon delivery.

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