Principal Engineer-Design

FHLB Des Moines

Chandler, Northern (AZ, KY)

Hybrid

USD 75,000 - 232,000

Full time

14 days+
Application generator

Don’t send a generic resume — generate a resume and cover letter tailored to this exact role.

Get past ATS filters

Benefits offered by this job

Health benefits from day one
ESPP with 2-year look-back
Retirement savings plan

Job summary

Microchip Technology Inc. is seeking a Principal Digital Design Engineer to lead RTL development and SoC integration for mixed-signal microcontrollers. You will drive digitals from concept to tape-out, mentor teams, and collaborate with analog, architecture, and product groups.

The role requires 10+ years in ASIC/SoC design and verification, strong RTL skills, and experience with EDA flows. Hybrid/onsite options in the US support fast-paced silicon delivery.

Qualifications

  • B.S. in Electrical Engineering, Computer Engineering, or related field with 10+ years' experience in ASIC/SoC Digital Design and Verification.
  • Strong foundations in digital logic / finite state machine design, computer architecture, RTL coding, and SoC integration techniques.
  • Working knowledge of Physical Design / APR concepts and flows (synthesis, floorplanning, place-and-route, CTS, ECO).
  • Familiarity with industry EDA flows / tools (Cadence, Synopsys, Siemens), Linux, Windows.
  • Scripting skills (Python / Perl / Tcl) for productivity and flow automation.

Responsibilities

  • Own and drive digital block and subsystem design from concept through tape-out.
  • Develop high-quality RTL for digital peripherals and IP (8/32-bit blocks).
  • Lead block- and SoC-level verification and integration, including digital verification, UPF/low-power, AMS/mixed-signal collaboration, STA, and ECO support.

Skills

RTL design
Verilog/SystemVerilog
SoC integration
Digital verification
UPF & low-power
AMS/mixed-signal verification
STA
PD/Place & Route coordination
EDA tool flows
Python/Perl/Tcl

Education

B.S. in Electrical/Computer Engineering
M.S. preferred

Tools

Cadence
Synopsys
Siemens
Linux
Windows

Job description

People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our ; we affectionately refer to it as the *Aggregate System* and it’s won us countless awards for diversity and workplace excellence.Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over without a great team dedicated to empowering innovation. People like you.Visit our page to see what exciting opportunities and company await!**Job Description:**We’re looking for a highly motivated, creative Principal Digital Design Engineer to join our engineering team and lead development of digital IP and SoC-level integration for mixed-signal microcontrollers. This is a hands-on role spanning RTL design, integration, and signoff verification—with broad cross-functional exposure to analog, architecture, validation/test, and product teams.Key Responsibilities:* Own and drive digital block and subsystem design from concept through tape-out, partnering with architects and system engineers on definition and requirements* Develop high-quality RTL (Verilog / System Verilog) for digital peripherals and IP (8/32-bit class blocks), emphasizing robust, reusable design* Lead block- and SoC-level verification and integration, including: + Digital verification (simulation/regressions, assertions/coverage) + UPF / low-power intent integration and verification + AMS / mixed-signal verification collaboration with analog teams + Static Timing Analysis (STA) support and closure coordination + Power and IR analysis and support with implementation/signoff teams + Physical Design / APR (Place & Route) collaboration and signoff support, including synthesis handoff, floorplanning awareness, timing/DRC/LVS closure coordination, and ECO support with PD teams* Provide technical leadership via design reviews, documentation, debug leadership, and project planning* Collaborate closely with analog design, architecture, product and test engineering, applications, and marketing to ensure silicon and product success**Requirements/Qualifications:**Qualifications/Requirements* B.S. in Electrical Engineering, Computer Engineering, or related field with 10+ years' experience in ASIC/SoC Digital Design and Verification* Strong foundations in digital logic / finite state machine design, computer architecture, RTL coding, and SoC integration techniques* Working knowledge of Physical Design / APR concepts and flows (synthesis, floorplanning, place-and-route, CTS, ECO), and ability to partner effectively with PD teams on timing/power/DFM closure* Familiarity with industry EDA flows / tools (Cadence, Synopsys, Siemens), Linux, Windows* Scripting skills (Python / Perl / Tcl) for productivity and flow automation* Excellent debug, analytical thinking, and clear communication skills; comfortable driving alignment across teams* Thrives in a team-oriented, fast-paced environment with a strong ownership mindset and continuous learning attitudePreferred qualification:* M.S. in Electrical Engineering, Computer Engineering, or related field**Travel Time:**0% - 25%**Physical Attributes:**Hearing, Seeing, Talking**Physical Requirements:**80% sitting, 10% walking, 10% standing**Pay Range:**We offer a total compensation package that ranks among the best in the industry. It consists of competitive base pay, restricted stock units, and quarterly bonus payments. In addition to these components, our package includes health benefits that begin day one, retirement savings plans, and an industry leading ESPP program with a 2 year look back feature. Find more information about all our benefits at the link below:The annual base salary range for this position, which could be performed in the US, is $75,000- $232,000.\*\*Range is dependent on numerous factors including job location, skills and experience.Microchip Technology Inc is an equal opportunity/affirmative action employer. All qualified applicants will receive consideration for employment without regard to sex, gender identity, sexual orientation, race, color, religion, national origin, disability, protected Veteran status, age, or any other characteristic protected by law. For more information on applicable equal employment regulations, please refer to the .**To all recruitment agencies**: *Microchip Technology Inc. **does not** accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.*At Microchip, employees are our greatest strength. As one of the top performing semiconductor companies in the world, we are led by a set of guiding values and a mission to empower innovation to enhance the human experience. We work tirelessly to create a company culture that highlights how important every employee is to our mission.
Get your free, confidential resume review.

or drag and drop your file here.

Similar jobs

Similar jobs worth comparing

Principal Engineer-Design
Principal Engineer-Design

Microchip Technology Inc • Chandler (AZ)

On-site
USD 75,000 - 232,000
Health benefits from day one
ESPp program with 2 year look back
Technical Staff Engineer-Design (Digital Logic)
Technical Staff Engineer-Design (Digital Logic)

FHLB Des Moines • Colorado Springs (CO)

On-site
USD 91,000 - 232,000
Health benefits starting day one
Retirement savings plans
Quarterly bonus payments
Principal Engineer - Analog IP Tech Lead
Principal Engineer - Analog IP Tech Lead

FHLB Des Moines • Chandler (AZ)

On-site
USD 75,000 - 232,000
Principal Engineer - Digital Design
Principal Engineer - Digital Design

Microchip Technology Inc. • Colorado Springs (CO)

On-site
USD 75,000 - 232,000
Health benefits from day one
Retirement savings plans
ESPP program with 2-year look back
Senior Engineer I- Product
Senior Engineer I- Product

FHLB Des Moines • Chandler (AZ)

On-site
USD 90,000 - 130,000
Principal Engineer – Physical Design
Principal Engineer – Physical Design

FHLB Des Moines • Chandler (AZ), Northern (KY)

Hybrid
USD 140,000 - 190,000
Principal Engineer - Design
Principal Engineer - Design

FHLB Des Moines • Roseville (CA), Northern (KY)

Hybrid
USD 75,000 - 232,000
Health benefits from day one
RSU program
ESPP with 2-year look-back
Senior Engineer II - Design
Senior Engineer II - Design

FHLB Des Moines • Hauppauge (NY)

On-site
USD 75,000 - 205,000
Technical Staff Engineer - Applications
Technical Staff Engineer - Applications

FHLB Des Moines • San Jose (CA)

On-site
USD 91,000 - 232,000
Health benefits from day one
Quarterly bonus payments
Retirement savings plans
+1
Senior Engineer I - Product
Senior Engineer I - Product

FHLB Des Moines • Boulder (CO)

On-site
USD 70,000 - 205,000
Wellness & Medical Benefits
Quarterly Bonus
Restricted Stock Grant
+4