Principal DFT Engineer – Lead Tapeouts & Test Automation

SiTime Corporation; United States; On-site; USD 180,000 - 270,000; Full time

Job summary

SiTime Corporation seeks a seasoned Principal DFT Engineer to lead the DFT architecture, implementation, verification, and signoff of complex digital blocks and subsystems. The role owns DFT end-to-end from architecture through manufacturing support and signoff, shaping methodology and automation across programs.

You'll collaborate with RTL and Physical Design teams, drive ATPG, timing constraints, and post-silicon bring-up with product/test engineering teams while mentoring others and upholding

Qualifications

• MS in Electrical/Computer Engineering or related field with 10+ years, or PhD with 6+ years.

Responsibilities

• Lead architecture, implementation, verification, and signoff of DFT across programs.
• Define DFT architecture and specs including scan, compression, clocking, and test modes.
• Implement and validate DFT structures: scan insertion, OCC, compression like EDT/LPCT.
• Develop automated DFT flows: ATPG, verification, signoff.
• Own ATPG generation, pattern validation, fault analysis, coverage closure.
• Define, develop, and verify timing constraints for functional modes.
• Collaborate with RTL and Physical Design to resolve testability issues early.
• Work with ATE/test engineering to bring up patterns and diagnose failures.
• Not all requirements must be met; diverse experiences welcome.

Skills

DFT leadership

Scripting: Tcl/Perl/Python

Timing constraints

Education

MS in Electrical/Computer Engineering or related

PhD with 6+ years experience

Tools

Siemens Tessent

Synopsys TestMAX

Cadence Modus

Job description

SiTime Corporation seeks a seasoned Principal DFT Engineer to lead the DFT architecture, implementation, verification, and signoff of complex digital blocks and subsystems. The role owns DFT end-to-end from architecture through manufacturing support and signoff, shaping methodology and automation across programs.

You'll collaborate with RTL and Physical Design teams, drive ATPG, timing constraints, and post-silicon bring-up with product/test engineering teams while mentoring others and upholding