Principal DFT Engineer — Lead DFT Architecture & Signoff

SiTime Corporation; Tempe (AZ); Sur place; USD 161 000 - 230 000; Plein temps

Avantages offerts par ce poste

401k plan

Health and wellness benefits

Parental leave

Legal services

Time off plans

Résumé du poste

SiTime Corporation seeks a seasoned Principal DFT Engineer to own the DFT architecture, implementation, verification, and signoff of complex digital blocks and subsystems. You will lead end‑to‑end DFT, shape methodology, and establish best practices across programs.

You will partner with RTL, Physical Design, and ATE teams to bring up test patterns and diagnose failures, driving coverage and quality targets while mentoring teams and influencing engineering direction.

Qualifications

• MS/PhD in Electrical or Computer Engineering or related field with 10+ years experience, or PhD with 6+ years.
• Hands‑on DFT implementation and signoff through tape‑outs on advanced process nodes.
• Experience with DFT tools: Tessent, TestMAX, Modus.

Responsabilités

• Lead DFT architecture, implementation, verification and signoff reviews.
• Define DFT architecture and specifications including scan, test access, clocking, and core wrapping.
• Implement and validate digital DFT structures (scan insertion, compression, OCC).
• Develop automated DFT flows with ATPG, pattern validation and coverage closure.
• Collaborate with RTL and Physical Design to resolve testability issues early.

Connaissances

Scripting: Tcl/Perl/Python

DFT concepts & ATPG

Timing analysis & SDC

Cross‑functional communication

Analytical problem solving

English proficiency

Formation

MS in Electrical/Computer Engineering or related field

PhD with relevant experience (optional)

Outils

Siemens Tessent

Synopsys TestMAX

Cadence Modus

Description du poste

SiTime Corporation seeks a seasoned Principal DFT Engineer to own the DFT architecture, implementation, verification, and signoff of complex digital blocks and subsystems. You will lead end‑to‑end DFT, shape methodology, and establish best practices across programs.

You will partner with RTL, Physical Design, and ATE teams to bring up test patterns and diagnose failures, driving coverage and quality targets while mentoring teams and influencing engineering direction.