Principal Design Verification Engineer

OSI Engineering; San Jose (CA); Hybrid; USD 187,000 - 217,000; Full time

Job summary

A leading chip and silicon IP provider seeks a Principal Design Verification Engineer for its Memory Interface Chip team in San Jose. You will contribute to developing innovative products while collaborating with top engineering talent, driving verification for critical projects.

Qualifications

• Minimum 7 years industry experience outside of academia.
• Proficiency in Verilog, SystemVerilog, and UVM.
• Experience with code coverage and functional coverage closure.

Responsibilities

• Understand chip architecture and develop verification environments.
• Create test plans and develop test cases/sequences in UVM.
• Debug functional issues based on architectural specifications.

Skills

Communication

Problem-Solving

Team Collaboration

Education

Major in Electrical Engineering (EE) or Computer Science (CS)

Tools

Verilog

SystemVerilog

UVM

Linux

Job description

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A leading chip and silicon IP provider focused on accelerating and securing data is looking to hire an outstanding Principal Design Verification Engineer to join its Memory Interface Chip (MIC) team in San Jose, CA. This role offers the chance to work alongside top engineering talent on innovative products that push the boundaries of speed and data security.

As a Principal Design Verification Engineer, you’ll play a critical role in the development of MIC products. This is a full-time position reporting directly to the Senior Director of Analog Engineering. The MIC team is focused on advancing DIMM Interface Chips, and your work will be key to driving verification for PMIC, TS, and SPD projects.

Responsibilities:

• Understand the architecture of the chip and functional blocks.
• Develop/maintain verification environments for chip level verification and enhance/use the automated regression infrastructures.
• Create testplan and develop test cases/sequences in UVM.
• Debug functional issues in the DUT based on the good understanding of the architectural specification.
• Closely work with Design/Architecture/Circuit team to identify and align with the Milestones and Quality metrics of the project.

Requirements:

• Major in EE, CS or related.
• Min 7 years industry experience outside of academia
• Proficient in Verilog, systemverilog and UVM.
• Familiar with Linux environment and the industry’s prevailing EDA tools.
• Have better understanding of Verification methodology and concepts.
• Have good understanding of Pre-Silicon design process from Architecture, Design, Synthesis and Gate level Implementation till Tapeout release.
• Have excellent communication skills (both written and oral) and cross-team/function collaboration capability.
• Experienced in code coverage and functional coverage closure.
• Strong problem-solving skills.

Location: San Jose, CA, Hybrid

Salary Range: $187,000-217,000 (DOE)

Seniority level

• Seniority level

  Mid-Senior level

Employment type

• Employment type

  Full-time

Job function

• Industries

  Semiconductor Manufacturing and Engineering Services

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