Lead Design Verification Engineer (Networking)

SBT; San Francisco (CA); On-site; USD 150,000 - 190,000; Full time

Job summary

SBT is seeking a hands-on technical Design Verification Lead for a confidential company in the semiconductor industry. The role involves collaborating with systems engineers in developing cutting-edge computing systems, ensuring thorough validation of semiconductor designs, and building verification infrastructure. Ideal candidates have 5-10 years of experience and a master's degree in engineering.

Qualifications

• 5-10+ years of relevant industry experience.
• Expertise in network switching data paths related technology is preferred.

Responsibilities

• Develop verification plans and strategies based on design specifications.
• Define and develop a comprehensive suite of verification infrastructure.
• Collaborate with cross-functional teams to validate designs.

Skills

Verification Planning

SystemVerilog

UVM

Education

MS degree in relevant engineering field

Job description

14 hours ago Be among the first 25 applicants

President at SBT | 19 years of advising leaders in the semiconductor industry and architecting teams from startups to F500 companies

SBT is the exclusive executive recruiting firm for this confidential position.

This confidential company is strategically bringing on a hands-on technical DV lead. In this role, the verification expert will be collaborating cross-functionally with a talented team of systems HW engineers and SW architects in developing cutting-edge computing systems. This individual will have first-hand involvement in the full lifecycle of complex chip development, solving complex challenges directly affecting tier-one customers.

Technical Responsibilities

Verification Planning and Strategy

• Develop verification plans and strategies based on design specifications and requirements to ensure thorough testing and validation of semiconductor designs
• Create verification methodologies, test benches, and test cases to effectively verify and validate digital designs, including RTL (Register Transfer Level) designs

Building DV infrastructure

• Define and develop a comprehensive suite of verification infrastructure and tests that can be leveraged across both ASIC and FPGA platforms
• Collaborate with cross-functional teams to ensure that verification infrastructure and tests are aligned with design requirements and can be effectively used to validate designs

Qualifications

• MS degree in relevant engineering field
• 5-10+ years of relevant industry experience
• Proficiency in verification languages and methodologies, such as SystemVerilog, UVM
• Expertise in network switching data paths related technology is preferred

Seniority level

• Seniority level

  Mid-Senior level

Employment type

• Employment type

  Full-time

Job function

• Job function

  Engineering and Manufacturing

• Industries

  Semiconductor Manufacturing, Appliances, Electrical, and Electronics Manufacturing, and Computers and Electronics Manufacturing

Referrals increase your chances of interviewing at SBT by 2x

Sign in to set job alerts for “Design Verification Engineer” roles.

San Francisco, CA $150,000.00-$190,000.00 15 hours ago

Senior Innovation Manager, Acquisition and Engagement

San Francisco, CA $110,000.00-$140,000.00 12 hours ago

San Francisco, CA $150,000.00-$200,000.00 19 hours ago

San Francisco, CA $112,000.00-$160,000.00 1 day ago

Summer 2025 Intern - REWS Design and Delivery

San Francisco, CA $118,000.00-$172,000.00 1 day ago

Mechanical Design Engineer - Vehicle Interiors

South San Francisco, CA $100,000.00-$125,000.00 19 hours ago

Sunnyvale, CA $118,000.00-$172,000.00 1 day ago

San Francisco Bay Area $60,000.00-$70,000.00 18 hours ago

Mountain View, CA $40.00-$45.00 22 hours ago

South San Francisco, CA $115,000.00-$150,000.00 3 weeks ago

Library Aide #25C-6 (20572573)10-15 hours per week

We’re unlocking community knowledge in a new way. Experts add insights directly into each article, started with the help of AI.