Principal ASIC Verification Architect

Anysilicon; Austin (TX); On-site; USD 120,000 - 180,000; Full time

Job summary

Synopsys is seeking an experienced ASIC Digital Verification Engineer to join our team and contribute to the development of high-performance silicon chips and software content.

You will design and implement verification environments for Interface IP protocols, create test plans, develop and maintain verification IP and testbenches using SystemVerilog and UVM, and collaborate to resolve bugs while driving coverage closure.

Qualifications

• Extensive experience in ASIC digital verification.
• Experience with SystemVerilog and UVM methodologies.
• Strong understanding of digital design and verification concepts.

Responsibilities

• Design and implement verification environments for Interface IP protocols.
• Create and execute detailed test plans for complex ASIC designs.
• Develop and maintain verification IP and testbenches using SystemVerilog and UVM.
• Collaborate with design and architecture teams to identify and resolve bugs.
• Perform functional coverage analysis and drive coverage closure.

Skills

Detail-oriented

Analytical thinking

Communication

Team collaboration

Leadership

Tools

SystemVerilog

UVM

VCS

ModelSim

Job description

Synopsys is seeking an experienced ASIC Digital Verification Engineer to join our team and contribute to the development of high-performance silicon chips and software content.

You will design and implement verification environments for Interface IP protocols, create test plans, develop and maintain verification IP and testbenches using SystemVerilog and UVM, and collaborate to resolve bugs while driving coverage closure.