Sr. Staff AI Engineer, Silicon Design

Cognichip; Redwood City (CA); On-site; USD 150,000 - 200,000; Full time

Job summary

Cognichip is seeking a versatile Sr. Staff AI Engineer in Redwood City, California, to integrate Artificial Intelligence into the semiconductor design lifecycle. This role involves bridging ML research and hardware engineering, facilitating productivity gains in chip design.

Qualified candidates will have an M.S. or higher in Electrical Engineering or Computer Science and 7+ years of semiconductor industry experience. Responsibilities include leading the development of AI solutions to improve design efficiencies and collaborating with design teams.

Qualifications

• 7+ years of experience in the semiconductor or EDA industry.
• Proficiency in PyTorch or TensorFlow and experience in model evaluation tools.
• Strong programming skills in Python, C++, and SystemVerilog.

Responsibilities

• Design and deploy production‑scale generative workflows for EDA tasks.
• Architect foundation models to enhance the silicon design process.
• Collaborate with R&D and IP teams to embed AI into design flows.

Skills

Machine Learning

AI System Development

Programming in Python

Model Optimization

Kubernetes

Docker

Reinforcement Learning

Education

M.S. or higher in Electrical Engineering/Computer Science

Tools

PyTorch

TensorFlow

SystemVerilog

Job description

Sr. Staff AI Engineer, Silicon Design

Position Overview

We are seeking a versatile Sr. Staff AI Engineer to drive the integration of Artificial Intelligence into the semiconductor design lifecycle. In this role, you will bridge the gap between advanced ML research and production-grade hardware engineering, developing specialized foundational language models and cognitive orchestration systems that optimize everything from RTL generation to physical verification. You will be responsible for building practical, scalable AI solutions that provide measurable productivity gains in high‑stakes chip design environments.

Key Responsibilities

• AI System Development: Design and deploy production‑scale generative workflows and context‑augmented retrieval mechanisms to automate complex EDA tasks, including IP configuration and RTL generation.
• Model Optimization: Architect and fine‑tune foundation models (LLMs/SLMs) and other deep learning architectures to enhance the silicon design process.
• Reinforcement Learning: Implement Reinforcement Learning (RL) environments and policy‑gradient methods to guide non‑linear optimization routines across automated cell‑sizing and routing passes.
• End‑to‑End Flow Integration: Collaborate with R&D and IP teams to embed AI‑driven assistants directly into existing digital and analog design flows.
• Scalable Engineering: Build robust, cloud‑native training pipelines using Kubernetes and Docker to handle large‑scale EDA datasets.
• Technical Leadership: Lead the transition of AI prototypes into reliable tools, ensuring high performance, maintainability, and scalability for thousands of internal users.

Required Qualifications

• Education: M.S. or higher in Electrical Engineering, Computer Science, or a related field with a focus on AI/ML or VLSI.
• Professional Experience: 7+ years of experience in the semiconductor or EDA industry, with a proven track record of deploying AI/ML models in a production capacity.
• Broad EDA Knowledge: Hands‑on experience across the full silicon lifecycle (RTL‑to‑GDS), with specific exposure to Physical Design, Place‑and‑Route, and Physical Verification (DRC/LVS).
• Software Proficiency: Strong programming skills in Python, C++, and SystemVerilog, along with experience in scripting (Tcl, Shell).
• Machine Learning Stack: Proficiency in PyTorch or TensorFlow, and experience with state‑of‑the‑art framework orchestration, custom inference optimization tools, and model evaluation harnesses.

Preferred Qualifications & Skills

• Advanced Education: Ph.D. with research specifically focused on AI/ML for EDA and metric modeling.
• Practical Chip Design: Extensive experience with advanced technology nodes (7nm, 5nm, 3nm, or below) and physical verification toolsets (e.g., IC Validator, Calibre).
• Specialized ML: Demonstrated experience in Multi‑objective Optimization, Transfer Learning, and the application of machine learning architectures to hardware problems.
• Systems Engineering: Deep expertise in operationalizing GenAI platforms on distributed, multi‑GPU cloud environments.
• Hardware Acceleration: Background in optimizing algorithms for FPGA or SoC deployment and hardware‑efficient ML implementation.