Staff Chip Design Engineer

Cognichip, Inc.; Redwood City (CA); Hybrid; USD 180,000 - 240,000; Full time

Job summary

Cognichip, Inc. is seeking a Staff Chip Design Engineer to advance RTL design and ML-assisted silicon workflows in a hybrid Redwood City setting.

You will collaborate with ML and software teams to build scalable design-to-production pipelines and deliver end-to-end silicon solutions. Ideal candidates bring 10–15 years of RTL design or mixed design/verification experience, strong SystemVerilog and Python, and proven ability to communicate complex concepts across disciplines.

Qualifications

• Masters in Computer Science, Electrical Engineering, or closely related field.
• 10-15 years of RTL design experience or mix of design and verification.
• Proficiency in SystemVerilog and Python.
• Excellent written and verbal communication, especially cross-disciplinary.
• Experience in a dynamic, research-heavy startup environment.
• Courses or projects in machine learning / deep learning.

Responsibilities

• Serve as domain experts embedding chip design into AI chip design assistants.
• Bridge research and production; collaborate with ML and SW teams to integrate models into scalable pipelines.
• Define data-processing pipelines, training orchestration, and evaluation frameworks for large-scale experiments.
• Analyze large datasets, experimental logs, simulation outputs, and traces to diagnose model behavior and surface failures.
• Publish and present findings; contribute to open-source projects and share internally/externally.

Skills

RTL design

SystemVerilog

Python

Communication

Startup environment

ML coursework

Education

Master's degree in CS/EE

Tools

Verilator

CocoTB

Yosys

OpenSTA

PCIe

Vivado

Vitis

Quartus

Job description

Overview

At Cognichip, we’re not just building AI—we’re redefining what’s possible at the nexus of silicon design and machine learning. As a Staff Chip Design Engineer on our team, you’ll tackle real-world scientific and coding challenges—defining the processes for dataset collection, curation, and enhancement. You’ll fuse knowledge of chip design and ML into end-to-end silicon design flows. If you thrive on pushing the envelope of research and translating cutting-edge ideas into production-grade systems, this is your stage.

What you’ll do

• Serve as the domain experts, embedding chip design experience into a team creating AI chip design assistants
• Bridge research and production. Collaborate closely with ML and SW teams to integrate experimental models into scalable pipelines.
• Define data-processing pipelines, training orchestration, and evaluation frameworks to accelerate iteration on large-scale experiments.
• Analyze and iterate. Dive deep into large datasets—experimental logs, simulation outputs, and user interaction traces—to diagnose model behavior, surface failure modes, and drive evidence-based improvements.
• Publish and present. Document findings in technical reports, contribute to open-source projects, and present work internally (and externally, when appropriate) to help shape the broader AI research community.

What You Bring

• Masters in Computer Science, Electrical Engineering, or a closely related field
• 10-15 years of experience in RTL design, or a combination of design and verification
• Proficiency in SystemVerilog and Python languages
• Excellent written and verbal communication skills, esp to convey chip design knowledge to scientists/engineers in other fields
• Comfortable working in a dynamic, research-heavy startup environment
• Demonstrated coursework or project experience in machine learning and/or deep learning

Bonus Points

• Personal projects showcasing innovation, creativity, and continuous learning
• Knowledge of industry-standard communication protocols (SPI, I2C, AXI, Ethernet, PCIe, DDR5, etc)
• Knowledge of open-source tools and contribution practices (Verilator, CocoTB, Yosys, OpenSTA, etc)
• Experience with multiple areas of chip flow (RTL design, validation, synthesis, physical design, etc)
• Experience with FPGA development (Vivado, Vitis, Quartus, etc), front end, IP integration, and/or back end

What it's like here

We’re a fast-moving AI startup with a collaborative, high-trust culture. You’ll work with top-tier engineers, scientists, and builders—solving hard problems that sit at the intersection of cloud computing, AI, and chip design. We value technical excellence, ownership, and the freedom to experiment. If you’re excited to build the future of engineering, you’ll feel right at home.

Logistics

This position is available in Silicon Valley’s Redwood Shores, CA. We have a hybrid schedule with four days in office, one day remote. Cognichip accepts applications that need H1B transfer.