Principal Analog Design Leader for High-Speed SerDes & ICs

Astera Labs; Irvine, Northern (CA, KY); Hybrid; USD 170,000 - 210,000; Full time

Benefits offered by this job

Discretionary bonus

Benefits package

Job summary

Astera Labs in Irvine, CA is redefining connectivity for rack-scale AI infrastructure. As a Principal Analog Design Engineer, you will architect and design high-performance analog and mixed-signal circuits that anchor SerDes, PHY, and high-speed I/O in silicon, shaping power, performance, and reliability for data center deployments.

This hands-on, high-impact role requires guiding designs from concept through silicon bring-up, setting the technical bar for the analog team, and mentoring

Qualifications

• MS or PhD in Electrical Engineering or related field.
• 8+ years of experience in analog and mixed-signal IC design.
• Proven track record designing high-speed analog circuits (PLLs, SerDes, data converters, references, or regulators) in CMOS/FinFETs.
• Strong understanding of physical-layer design, signal integrity, and high-speed I/O.
• Proficient with Cadence Virtuoso/Spectre and layout-aware design.

Responsibilities

• Architect high-speed analog and mixed-signal circuits including PLLs, SerDes front-ends, data converters, references, and regulators.
• Drive design from specification through schematic, layout supervision, and verification across PVT corners.
• Develop robust designs in FinFET nodes with attention to power, area, and performance trade-offs.
• Lead silicon bring-up, characterization, and debug with validation and product engineering.
• Define and execute test plans to correlate silicon performance with targets.
• Set analog design methodology, review standards, and best practices across the team.
• Partner with digital, physical design, systems, and architecture teams; mentor junior engineers.
• Lead technical design reviews and foster a collaborative, ownership-driven culture.

Skills

Analog design

Mixed-signal design

PLL design

SerDes

High-speed I/O

Signal integrity

Cadence tools

Education

MS/PhD in Electrical Engineering

Tools

Cadence Virtuoso

Cadence Spectre

Job description

Astera Labs in Irvine, CA is redefining connectivity for rack-scale AI infrastructure. As a Principal Analog Design Engineer, you will architect and design high-performance analog and mixed-signal circuits that anchor SerDes, PHY, and high-speed I/O in silicon, shaping power, performance, and reliability for data center deployments.

This hands-on, high-impact role requires guiding designs from concept through silicon bring-up, setting the technical bar for the analog team, and mentoring