Senior High-Speed Analog Layout Lead for IP Blocks

Celero Communications; Irvine (CA); On-site; USD 150,000 - 250,000; Full time

Benefits offered by this job

Foundational role

Cross-functional teams

International culture

Growth with Celero

Job summary

Celero Communications is a fast-growing semiconductor startup seeking a High-Speed Analog Layout Design Engineer to lead the physical layout of ADCs, DACs, PLLs and other high-performance analog/mixed-signal circuits.

You will interface with circuit designers, CAD/PDK teams, and layout engineers across time zones, mentoring junior staff and ensuring first-pass silicon success in a fast-paced environment.

Qualifications

• 10+ years hands-on analog/mixed-signal layout experience in advanced CMOS/FinFET technologies.
• Leadership in owning major IP layout macros or full-chip layouts at FinFET nodes (TSMC preferred).
• Experience with LVS/DRC checks and signoff flows, and collaborating with cross-functional teams.

Responsibilities

• Lead physical layout design of analog/mixed-signal macros from floor planning to final verification.
• Collaborate with schematic designers to optimize performance, matching, symmetry, and reliability.
• Mentor junior layout engineers across multiple time zones and enforce best practices.

Skills

Analog layout

Mixed-signal design

Floor planning

LVS/DRC/PERC/ERC

IP/layout leadership

Tools

Cadence Virtuoso

Calibre

Pegasus

Job description

Celero Communications is a fast-growing semiconductor startup seeking a High-Speed Analog Layout Design Engineer to lead the physical layout of ADCs, DACs, PLLs and other high-performance analog/mixed-signal circuits.

You will interface with circuit designers, CAD/PDK teams, and layout engineers across time zones, mentoring junior staff and ensuring first-pass silicon success in a fast-paced environment.