Pre-Silicon Memory Verification Engineer - Hybrid (UVM)

Solidigm; Rancho Cordova (CA); Hybrid; USD 121,000 - 194,000; Full time

Benefits offered by this job

RSU

RCU

Cash bonus

Job summary

Solidigm in Rancho Cordova, CA seeks a pre-silicon verification engineer for advanced 3D NAND designs. You will implement UVM-based tests, define functional coverage, and develop SystemVerilog Assertions to ensure thorough validation of complex memory components.

The role involves building mixed-signal models and full-chip verification environments, plus automation tools to streamline workflows and data collection. Hybrid work arrangement in California is available.

Qualifications

• Master’s degree in a relevant field with 3+ years (or Bachelor’s with 5+ years).
• Experience in pre-silicon verification of memory products required.
• Proficient with UVM, SystemVerilog Assertions, and formal verification.
• Experience with mixed-signal modeling and simulations.

Responsibilities

• Create and maintain verification test plans based on design specifications.
• Develop UVM-based directed and constrained-random tests, debug simulation failures, and quickly identify design, testbench, or test issues.
• Define functional coverage models and perform coverage analysis and closure.
• Create and maintain SystemVerilog Assertions (SVA) for 3D NAND designs based on verification requirements.
• Develop, maintain, and enhance the UVM-based verification environment to support evolving design and verification requirements.
• Develop and maintain mixed-signal full-chip models and verification environments, including analog behavioral models, cell-level testbenches, and full-chip mixed-signal netlists and testbenches.
• Develop scripts and tools to automate verification workflows, regression execution, results processing, and data collection.

Skills

UVM

SVA

Formal verification

Mixed-signal verification

Automation scripting

Education

Master’s degree in Electrical Engineering

Bachelor’s degree in Electrical/Computer Engineering

Tools

Python

Perl

Shell scripting

Job description

Solidigm in Rancho Cordova, CA seeks a pre-silicon verification engineer for advanced 3D NAND designs. You will implement UVM-based tests, define functional coverage, and develop SystemVerilog Assertions to ensure thorough validation of complex memory components.

The role involves building mixed-signal models and full-chip verification environments, plus automation tools to streamline workflows and data collection. Hybrid work arrangement in California is available.