Senior IP Logic Design Engineer, 3D NAND

Solidigm Inc.; Rancho Cordova (CA); Sur place; USD 105 440 - 164 800; Plein temps

Résumé du poste

Solidigm Inc. seeks a 3D NAND IP Logic Design Engineer to help shape the future of memory technology in its Rancho Cordova, CA location. You will architect, design, verify logic and circuit blocks for 3D NAND components, implement RTL in SystemVerilog, and drive sign-off with timed constraints and ECOs.

You will develop microcode-based 3D NAND algorithms, collaborate with pre-silicon verification, and support post-silicon debug across configurations to optimize density, performance, and cost.

Qualifications

• MS in electrical or computer engineering with 7+ years of experience, or BS with 9+ years of experience.
• Proven expertise in Verilog and SystemVerilog, with deep understanding of ASIC design flow: RTL design, logic synthesis, STA, ECO.
• Experience with lint tools, CDC/RDC analysis, and timing constraints.
• Strong background in design verification tools and automation scripting.
• Prior experience in 3D NAND Flash Memory logic design is a plus.
• Ability to work independently across pre- and post-silicon debug cycles.

Responsabilités

• Architect, design, and verify logic and circuit blocks for 3D NAND flash memory components.
• Define micro-architecture specifications, implement RTL in SystemVerilog, generate synthesis netlists with constraints, perform STA, resolve violations, implement ECOs, drive sign-off.
• Develop and optimize microcode-based 3D NAND algorithms using proprietary instruction sets and compilers.
• Contribute to next-gen 3D NAND architecture and improve density, die-size, performance, power, and cost.
• Collaborate with pre-silicon verification to build unit-level test benches, implement SVAs, run RTL and GLS regressions, ensure functional and code coverage.
• Review pre-silicon AMS simulations and post-silicon waveforms for power & performance modeling.
• Partner with product engineering and technology development to define Read-Window-Budget features and DAC/DFT methods.
• Support post-silicon debug and failure analysis across configurations.

Connaissances

Verilog

SystemVerilog

ASIC design flow

RTL design

STA

ECOs

design verification tools

automation scripting

Formation

MS in electrical engineering

7+ years experience

BS with 9+ years experience

Outils

lint tools

CDC/RDC analysis

timing constraints

Description du poste

Solidigm Inc. seeks a 3D NAND IP Logic Design Engineer to help shape the future of memory technology in its Rancho Cordova, CA location. You will architect, design, verify logic and circuit blocks for 3D NAND components, implement RTL in SystemVerilog, and drive sign-off with timed constraints and ECOs.

You will develop microcode-based 3D NAND algorithms, collaborate with pre-silicon verification, and support post-silicon debug across configurations to optimize density, performance, and cost.