Senior 3D NAND IP Logic Design Engineer

SmartRecruiters, Inc.; Rancho Cordova (CA); On-site; USD 105,000 - 165,000; Full time

Job summary

Solidigm, headquartered in Rancho Cordova, CA, is seeking a 3D NAND IP Logic Design Engineer to shape the future of memory technology. You will architect, design, and verify logic blocks for 3D NAND flash components and drive pre-silicon and post-silicon activities.

The role requires deep Verilog/SystemVerilog expertise, strong ASIC flow knowledge, and hands-on experience with verification tools and ECOs. Collaboration across teams to optimize density, performance, and power, while contributing

Qualifications

• MS in electrical or computer engineering with 7+ years experience, or BS with 9+ years.
• Proven expertise in Verilog and SystemVerilog; deep understanding of ASIC design flow.
• Experience with lint tools, CDC/RDC analysis, and timing constraints.
• Strong background in design verification tools and automation scripting.
• Prior experience in 3D NAND Flash Memory logic design is a plus.
• Ability to work independently across pre- and post-silicon debug cycles.

Responsibilities

• Architect, design, and verify logic and circuit blocks for 3D NAND flash memory components
• Define micro-architecture specifications, implement RTL in SystemVerilog, generate synthesis netlists with appropriate constraints, perform static timing analysis, resolve violations, implement ECOs, and drive design sign-off
• Develop and optimize microcode-based 3D NAND algorithms (read, program, erase, power-on) using proprietary instruction sets and compilers
• Contribute to next-gen 3D NAND architecture and pathfinding to improve density, die-size, performance, power, and cost
• Collaborate with pre-silicon verification teams to build unit-level test benches, implement SystemVerilog Assertions (SVAs), run full-chip RTL and gate-level simulation (GLS) regressions, and ensure functional and code coverage for various read-window-budget and customer features
• Review pre-silicon analog and mixed signal (AMS) simulations and post-silicon microprobe waveforms to conduct power & performance modeling and ensure the functionality of various digital & analog blocks
• Partner with product engineering and technology development teams to define Read-Window-Budget (RWB) features and develop Design for Testability (DFT) methods that reduce test time and cost while improving quality
• Support post-silicon debug and failure analysis across multiple configurations

Skills

Verilog

SystemVerilog

ASIC design flow

RTL design

Synthesis & STA

ECOs

Verification tooling

Scripting

3D NAND Flash

Education

MS in Electrical or Computer Engineering

BS in Electrical or Computer Engineering

BS in Electrical/Computer Engineering

Tools

Lint tools

CDC/RDC analysis

Timing constraints tooling

SVAs (SystemVerilog Assertions)

RTL/GLS simulations tooling

Job description

Solidigm, headquartered in Rancho Cordova, CA, is seeking a 3D NAND IP Logic Design Engineer to shape the future of memory technology. You will architect, design, and verify logic blocks for 3D NAND flash components and drive pre-silicon and post-silicon activities.

The role requires deep Verilog/SystemVerilog expertise, strong ASIC flow knowledge, and hands-on experience with verification tools and ECOs. Collaboration across teams to optimize density, performance, and power, while contributing