Power Integrity & EM Signoff Engineer for Next-Gen SoCs

Watershed

Palo Alto (CA)

In loco

USD 237.000 - 296.000

Tempo pieno

14 giorni+

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Descrizione del lavoro

Rivian is seeking a highly skilled Physical Design Engineer specializing in Power Integrity (PI) and Signoff Analysis. You will ensure electrical reliability of next-generation SoCs, bridging physical implementation and electrical verification.

Responsibilities include static/dynamic IR drop, EM analysis, and PI signoff for advanced nodes. You will develop automation scripts (Tcl/Python), stay current with EDA tools, and collaborate with PD, RTL, and packaging teams to optimize PG density and

Competenze

BS/MS in Electrical Engineering.
10+ years of extensive physical design experiences at block/sub-chip/full-chip level is a plus.
Deep understanding of PDN and the physics of IR drop.
Proficiency in PI/Signoff tools: RedHawk-SC, Voltus, PrimePower/Rail.
Experience with UPF power intent and MSV designs.

Mansioni

Perform Static IR Drop analysis to validate power grid robustness.
Conduct Dynamic Voltage Drop analysis to identify hotspots during peak activity.
Collaborate with RTL/Architecture to optimize power at block and top levels.
Execute EM and Power EM analysis for long-term reliability.
Drive the PI signoff flow for deep sub-micron nodes (5nm, 3nm).