Senior PI & EM Signoff Engineer for Next-Gen SoCs

Rivian; Palo Alto (CA); On-site; USD 237,000 - 296,000; Full time

Benefits offered by this job

401(k) Plan

Employee Stock Purchase Program

Comprehensive benefits package

Job summary

Rivian is seeking a highly skilled Physical Design Engineer focused on Power Integrity and Signoff Analysis. You will ensure electrical reliability of next-gen SoCs, bridging physical implementation with electrical verification and leading to successful tapeouts.

You will perform IR drop and EM analyses, optimize PDN, and develop automation scripts, collaborating closely with RTL, Architecture and PD teams. This role targets senior professionals with extensive PI/EM-IR expertise.

Qualifications

• BS or MS in Electrical Engineering.
• 10+ years of extensive physical design experience at block/sub-chip and ideally full-chip level.
• Strong knowledge of PDN, IR drop physics, PI/Signoff requirements.
• Proficiency with PI/Signoff tools: RedHawk-SC, Voltus, PrimePower/Rail.
• Experience with MSV designs and UPF power intent.
• Programming: Tcl, Python, or Perl for flow automation.
• Cross-functional collaboration across Front-end, PD and Package teams.

Responsibilities

• Perform Static IR Drop analysis to validate power grid connectivity.
• Conduct Dynamic Voltage Drop analysis to identify hotspots during peak bursts.
• Collaborate with RTL/Architecture to optimize power at block and top levels.
• Execute EM analysis and fixes to ensure long-term reliability and signoff.
• Drive PI signoff for deep sub-micron nodes and assess decap impact on noise.
• Develop automation scripts (Tcl/Python) to streamline PI analysis and reporting.

Skills

Power Integrity

EM-IR sign-off

RedHawk-SC

Voltus

PrimePower/Rail

Tcl/Python scripting

UPF power intent

PM/flow automation

Education

BS/MS in Electrical Engineering

Tools

Ansys RedHawk-SC

Cadence Voltus

Synopsys PrimePower/Rail

UPF tooling

Job description

Rivian is seeking a highly skilled Physical Design Engineer focused on Power Integrity and Signoff Analysis. You will ensure electrical reliability of next-gen SoCs, bridging physical implementation with electrical verification and leading to successful tapeouts.

You will perform IR drop and EM analyses, optimize PDN, and develop automation scripts, collaborating closely with RTL, Architecture and PD teams. This role targets senior professionals with extensive PI/EM-IR expertise.