Lead Power Integrity Engineer

Primis; Austin (TX); On-site; USD 140,000 - 210,000; Full time

Job summary

Primis in Austin, TX is seeking a seasoned power integrity engineer to lead IR drop, electromigration, and PDN analysis on advanced chip programs. You will apply deep hands-on expertise in IR drop, EM, and PDN architecture to push issues to resolution with physical design and signoff teams.

This high-ownership role collaborates across physical design, implementation, timing, RTL, package, and system engineering, building automation with Tcl/Python/Perl, mentoring peers, and refining signoff

Qualifications

• 8–15 years in ASIC/semiconductor design, physical design, or power signoff disciplines.
• Deep hands-on IR drop, EM, and power integrity experience.
• Fluency with power integrity/signoff tools: Ansys RedHawk-SC, Cadence Voltus, or equivalent.
• Tcl/Python/Perl scripting for flow automation.
• Strong problem-solving and cross-functional communication.

Responsibilities

• Lead power integrity and analysis work from implementation through signoff close.
• Run static and dynamic IR/voltage-drop studies across operating modes and PVT corners.
• Own electromigration analysis and power-grid reliability signoff.
• Analyze and tune power distribution network architecture; flag integrity risk early.
• Debug voltage-drop and EM failures and drive fixes with physical design.
• Characterize chip- and block-level power, dynamic and leakage.
• Coordinate with physical design, STA, package, and systems teams on power delivery challenges.
• Refine power analysis methodology, flows, and signoff criteria.
• Build automation and analysis scripts in Tcl, Python, or Perl.
• Brief technical leadership on findings, risk, and recommendations.
• Mentor engineers on power and physical signoff topics.

Skills

IR drop

EM analysis

Power integrity

Scripting

Crossfunctional

Signoff

Education

BS/MS in EE/CE

Tools

Ansys RedHawk-SC

Cadence Voltus

Job description

We're hiring a seasoned power integrity engineer to lead voltage-drop, electromigration, and power-network analysis on advanced chip programs. You'll bring hands-on depth in IR drop, EM, PDN architecture, and static/dynamic voltage analysis, plus the ability to push issues to resolution alongside physical design and signoff teams.

This is a high-ownership role that works closely with physical design, implementation, timing, RTL, package, and system engineering functions.

What You'll Do

• Lead power integrity and analysis work from implementation through signoff close.
• Run static and dynamic IR/voltage-drop studies across operating modes and PVT corners.
• Own electromigration analysis and power-grid reliability signoff.
• Analyze and tune power distribution network architecture; flag integrity risk early.
• Debug voltage-drop and EM failures and drive fixes with physical design.
• Characterize chip- and block-level power, dynamic and leakage.
• Reconcile power numbers across RTL, synthesis, implementation, and signoff stages.
• Balance power optimization against timing, area, reliability, and performance.
• Evaluate power-domain behavior under different workload and activity scenarios.
• Coordinate with physical design, STA, package, and systems teams on power delivery challenges.
• Refine power analysis methodology, flows, and signoff criteria.
• Build automation and analysis scripts in Tcl, Python, or Perl.
• Brief technical leadership on findings, risk, and recommendations.
• Mentor engineers on power and physical signoff topics.

What You Bring

• 8–15 years in ASIC/semiconductor design, physical design, or power signoff disciplines.
• Deep hands-on IR drop, EM, and power integrity experience.
• Strong grasp of static/dynamic voltage drop, EM mechanics, and power-grid design.
• Fluency with industry power integrity/signoff tools: Ansys RedHawk-SC, Cadence Voltus, or equivalent.
• Solid understanding of ASIC physical implementation and signoff flows.
• Experience isolating dynamic and leakage power drivers.
• Understanding of PVT, mode, and activity-factor dependent power behavior.
• Comfort debugging complex power integrity issues through to implementation fixes.
• Tcl/Python/Perl scripting for flow automation.
• Strong problem-solving and cross-functional communication.

Nice to Have

• Advanced-node, high-performance SoC experience.
• Full-chip power integrity signoff ownership.
• Package/board power delivery and system-level power integrity knowledge.
• Power-aware implementation experience.
• Understands timing/power tradeoffs and the STA–PD–PI interaction.
• Has built or improved signoff methodology or automation.
• Technical leadership or mentoring background.
• BS/MS in Electrical Engineering, Computer Engineering, or related field

ADVERT DISCLAIMER

Research indicates that men will apply to a role when they only meet 50-60% of the descriptions, however, when looking at women and other minority groups, they can look for up to a 99% match in order to apply to a role. If you feel you are a fit for our role, please still apply, don’t worry if you don’t tick every single box. We’d still love to hear from you. We encourage underrepresented talent to apply to all our roles & support accessibility needs