Advanced Power Integrity & Power Delivery Architect

Rivian; Palo Alto (CA); On-site; USD 160,000 - 260,000; Full time

Job summary

Rivian in Palo Alto, CA is seeking a highly skilled Power Integrity & Power Architecture Engineer to lead end-to-end design, modeling, simulation, and post-silicon validation of advanced SoC power delivery architectures. You will bridge SoC design, power architecture, silicon packaging, and system-level PI.

You will collaborate across PDN, power supplier architectures, and packaging to ensure robust PI, efficiency, and thermal limits while optimizing power delivery across SoC, package, and board.

Responsibilities

• Power Delivery Network (PDN) architecture definition and optimization across SoC, packaging and board.
• Define requirements and simulation flows for power suppliers (IVRs, integrated switching regulators) for high efficiency and tight transient targets.
• SoC integration with silicon packaging, interposers and embedded passives to ensure robust PI.
• Pre- and post-layout PI/SI/IR/droop simulations across multiple domains.

Job description

About Rivian

Rivianis on a mission to keep the world adventurous forever. This goes for the emissions-free Electric Adventure Vehicles we build, and the curious, courageous souls we seek to attract.

As a company, we constantly challenge what's possible, never simply accepting what has always been done. We reframe old problems, seek new solutions and operate comfortably in areas that are unknown. Our backgrounds are diverse, but our team shares a love of the outdoors and a desire to protect it for future generations.

Role Summary

We are seeking a highly skilled and motivated Power Integrity & Power Architecture Engineer to lead the end-to-end design, modeling, simulation, and post-silicon validation of advanced SoC power delivery architectures. In this role, you will bridge the gap between System-on-Chip (SoC) design, power architecture, silicon packaging, and system-level power integrity.

Responsibilities

• Power Delivery Network (PDN) & Architecture: Define and optimize overall SoC power architecture, establishing target impedance, transient droop specifications, and efficiency targets across the full path: SoC/Packaging/Board.
• Advanced Power Supplier Architecture: Define requirements and simulation flows for next-generation power supplier architectures, such as IVRs, integrated switching regulators. Co-optimize power delivery for high efficiency, low supply ripple, tight transient droop targets, and strict thermal limits across the SoC, package and system.
• SoC Integration: Perform co-design and co-optimization for silicon packaging, interposers, embedded passives to ensure robust power integrity.
• Multi-Domain Modeling: Conduct pre- and post-layout power integrity (PI), signal integrity (SI), and IR/droop simulations using