Power & Clocking Architect for RISC-V SoCs

SiFive; Austin (TX); On-site; USD 206,000 - 251,000; Full time

Benefits offered by this job

Health, vision and dental benefits

Flexible paid time off

401(k) plan

Employee stock option program

Job summary

SiFive is seeking a Power-Management/Reset/Clock Micro-Architect and RTL Design Engineer to design CPU cores and interconnect IP for open RISC-V based SOCs. You will implement PM, reset, and clocking solutions, with a focus on high performance and configurability, delivering hardware with software-like agility.

You will collaborate with architecture, verification, and physical design teams to ensure quality, timing, and power goals are met while enabling time-to-market advantages for custom IP

Qualifications

• 3+ years of CPU/SoC clocking, reset, and power-management design experience.
• Experience in high-performance, energy-efficient CPU/SoC designs.
• Proficiency with RTL design in Verilog, SystemVerilog, or VHDL.
• Knowledge of RTL quality checks like Lint, CDC, RDC; Spyglass a plus.

Responsibilities

• Define power management requirements with the architecture team.
• Architect, design and implement core clocking, reset and power management solutions.
• Microarchitecture development and documentation through clear specs.

Skills

Power management

Reset design

Clocking design

DVFS

RTL design

Verilog/SystemVerilog

DFT/MBIST

Hardware debugging

Education

BS/MS degree in EE, CE, CS or related

Tools

Verilog

SystemVerilog

VHDL

Job description

SiFive is seeking a Power-Management/Reset/Clock Micro-Architect and RTL Design Engineer to design CPU cores and interconnect IP for open RISC-V based SOCs. You will implement PM, reset, and clocking solutions, with a focus on high performance and configurability, delivering hardware with software-like agility.

You will collaborate with architecture, verification, and physical design teams to ensure quality, timing, and power goals are met while enabling time-to-market advantages for custom IP