Power‑Management CPU Architect & RTL Design Engineer

SiFive, Inc.; Santa Clara (CA); On-site; USD 158,760 - 194,040; Full time

Benefits offered by this job

Comprehensive medical, vision, dental benefits

401(k) plan with company match

Flexible paid time off

Employee stock option program

Job summary

SiFive, Inc. seeks a Power‑Management/Reset/Clock Micro‑Architect and RTL Design Engineer in Santa Clara to design leading CPU and interconnect IP. You will collaborate with various teams to define specifications and optimize power-management features, ensuring high-quality design and performance.

The ideal candidate will have a BS/MS in EE, CE, or CS, and be proficient in RTL design with 3+ years experience in CPU or SoC design. The role offers a salary range of $158,760 – $194,040 and comprehensive benefits.

Qualifications

• 3+ years recent industry experience in CPU and SoC clocking, reset, and power-management design.
• Expertise in CPU power state management and dynamic voltage/frequency scaling.
• Background in successful CPU or SoC development from architecture through tapeout.

Responsibilities

• Work with the architecture team to define power-management requirements.
• Design and implement core clocking and reset solutions.
• Collaborate with the physical implementation team to optimize designs.

Skills

CPU and SoC clocking

Reset control and design strategies

Power state definition and management

Dynamic voltage and frequency scaling (DVFS)

RTL design in Verilog, SystemVerilog, or VHDL

Attention to detail

Teamwork and communication skills

Object-oriented programming knowledge

Education

BS/MS degree in EE, CE, CS or related discipline

Tools

Spyglass

Git/GitHub

Jira

Confluence

Job description

SiFive, Inc. seeks a Power‑Management/Reset/Clock Micro‑Architect and RTL Design Engineer in Santa Clara to design leading CPU and interconnect IP. You will collaborate with various teams to define specifications and optimize power-management features, ensuring high-quality design and performance.

The ideal candidate will have a BS/MS in EE, CE, or CS, and be proficient in RTL design with 3+ years experience in CPU or SoC design. The role offers a salary range of $158,760 – $194,040 and comprehensive benefits.