CPU Power-Management Design Engineer

SiFive; Boston (MA); On-site; USD 100,000 - 130,000; Full time

Benefits offered by this job

Flexible paid time off

Health benefits

401(k) plan

Employee stock option program

Job summary

A leading tech company in Boston is looking for a hardware engineer to design industry-leading CPU and interconnect IP for RISC-V adoption. Responsibilities include architecting power management solutions, collaborating with verification teams, and implementing design strategies. Ideal candidates have 3+ years of experience in CPU designs, proficiency in Verilog/SystemVerilog, and a team-oriented mindset. The position offers flexible paid time off, health benefits, and other competitive perks.

Qualifications

• 3+ years of experience in CPU and SoC clocking, reset, and power-management logic designs.
• Proficiency with Verilog, SystemVerilog, or VHDL.
• Background in successful CPU or SoC development from architecture through tapeout.

Responsibilities

• Work with architecture team to understand power management requirements.
• Design clocking, reset, and power management solutions.
• Perform sandbox verification and collaborate on verification plans.

Skills

CPU design

SoC architecture

Power management

Verilog/SystemVerilog

Attention to detail

Team-oriented mindset

Education

BS/MS degree in EE, CE, CS or related field

Tools

Git/Github

Jira

Confluence

Job description

Overview

SiFive is the pioneer that introduced RISC-V to the world. We are transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications. SiFive’s compute platforms enable leading technology companies to innovate, optimize and deliver advanced solutions across chip design markets, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits. We are always excited to connect with talented individuals who are passionate about driving innovation and changing the world.

Our constant innovation and ongoing success come from amazing teams of highly capable people who collaborate and support each other to create truly groundbreaking ideas and solutions with real impact.

The Role

SiFive is looking for hardware engineers who are passionate about designing industry-leading CPU and interconnect IP to drive the adoption of RISC-V as the architecture of choice for SOC designs across vertical applications. We are creating highly configurable IP and improving time-to-market by designing hardware as configurable generators, leveraging software-like agility in hardware design.

As a Power-Management/Reset/Clock Micro-Architect and RTL Design Engineer, you will join a team of engineers dedicated to designing industry-leading CPU cores and subsystems based on RISC-V and TileLink. You will create power management, reset, and clocking solutions that act as the central nervous system for cutting-edge CPU and SoC IP designs, in a fast-paced environment aimed at delivering high quality and performance. Join us and surf the RISC-V wave with SiFive!

Responsibilities

• Work with the architecture team to understand and define power management requirements.
• Architect, design and implement core clocking, reset and power management solutions.
• Microarchitecture development and specification, with clear documentation and collaborative design culture.
• Perform initial sandbox verification and collaborate with the verification team to create and execute thorough verification plans.
• Collaborate with the physical implementation team to meet frequency, area, and power goals.
• Work with software teams to enable and optimize power management features.

Requirements

• 3+ years of experience in CPU and SoC clocking, reset, and power-management logic designs.
• Experience in high-performance, energy-efficient CPU and SoC designs.
• Expertise in CPU and SoC clocking, reset design, and power management, including:
• Reset control and design strategies: clock distribution, dynamic clocking, clock gating, and boundary crossing
• Power state definition and PMU design
• Dynamic and static power reduction techniques, including retention and power-up/down sequencing
• DVFS and Di/dt mitigation strategies
• Understanding of DFT, MBIST, Debug and error handling in CPU designs
• Power-aware simulation
• Proficiency with hardware (RTL) design in Verilog, SystemVerilog, or VDHL.
• Good understanding of RTL quality checks (Lint, CDC, RDC, etc.). Hands-on Spyglass is a plus.
• Attention to detail and a focus on high-quality design.
• Team-oriented mindset with collaborative engineering approach.
• Knowledge of at least one object-oriented and/or functional programming language.
• Background of successful CPU or SoC development from architecture through tapeout.
• BS/MS degree in EE, CE, CS or related technical discipline, or equivalent experience.

Nice to have

• Experience with AMBA Interconnect Protocols (AXI, AHB, APB).
• Experience with AMBA Low Power Protocol Interface, including P-channel and Q-channel.
• Experience with Scala/Chisel, Bluespec, or other hardware/software DSLs.
• Knowledge of RISC-V architecture.
• Experience with Git/Github, Jira, Confluence.

Pay & Benefits

SiFive is an equal employment opportunity workplace. We offer a competitive compensation package that includes flexible paid time off, health, vision and dental benefits, a 401(k) plan, employee stock option program, and more. This position requires a successful background and reference checks and proof of your right to work in the United States. The base pay range is a guideline and may vary by location and experience; the listed range is for the U.S. market. In addition to base pay, this role may include variable/incentive compensation and/or equity, and a comprehensive benefits package.

Equal Opportunity

SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. We are an E-Verify employer and comply with applicable regulations. California residents: see our job candidate notice for information on privacy rights and our Privacy Policy.