Power & Clock Architect for RISC-V SoCs

SiFive; Santa Clara (CA); On-site; USD 206,000 - 251,000; Full time

Benefits offered by this job

Healthcare and dental benefits

Flexible paid time off

401(k) plan

Employee stock option program

Job summary

SiFive is seeking hardware engineers passionate about CPU and interconnect IP to accelerate the adoption of RISC‑V across SOCs. You will help design power management, reset, and clocking solutions and contribute to high-performance CPU cores and subsystems using open RISC‑V and TileLink architectures.

You will join a fast-paced team delivering hardware that matches software speed in terms of reliability, performance, and configurability, with a focus on silicon quality and market impact.

Qualifications

• 3+ years of CPU/SoC clocking, reset, and power-management design experience.
• Experience in high-performance, energy-efficient CPU/SoC designs.
• Expertise in reset design, clocking, PMU design, and related techniques.
• Proficiency with RTL design in Verilog/SystemVerilog/VDHL.
• Knowledge of DFT/MBIST/Debug and power-aware simulation.

Responsibilities

• Define and implement core clocking, reset, and power management solutions.
• Develop microarchitecture and document design decisions clearly.
• Perform sandbox verification and collaborate on full verification plans.
• Coordinate with physical implementation to optimize timing, area, and power.
• Collaborate with software teams to enable power-management features.

Skills

CPU clocking

Power management

RTL design

Verilog/SystemVerilog

DVFS

Education

BS/MS EE/CE/CS

Tools

Git/Github

Jira

Confluence

Spyglass

Job description

SiFive is seeking hardware engineers passionate about CPU and interconnect IP to accelerate the adoption of RISC‑V across SOCs. You will help design power management, reset, and clocking solutions and contribute to high-performance CPU cores and subsystems using open RISC‑V and TileLink architectures.

You will join a fast-paced team delivering hardware that matches software speed in terms of reliability, performance, and configurability, with a focus on silicon quality and market impact.