CPU Power-Management Design Engineer

SiFive, Inc.; Santa Clara (CA); On-site; USD 158,760 - 194,040; Full time

Benefits offered by this job

Comprehensive medical, vision, dental benefits

401(k) plan with company match

Flexible paid time off

Employee stock option program

Job summary

SiFive, Inc. seeks a Power‑Management/Reset/Clock Micro‑Architect and RTL Design Engineer in Santa Clara to design leading CPU and interconnect IP. You will collaborate with various teams to define specifications and optimize power-management features, ensuring high-quality design and performance.

The ideal candidate will have a BS/MS in EE, CE, or CS, and be proficient in RTL design with 3+ years experience in CPU or SoC design. The role offers a salary range of $158,760 – $194,040 and comprehensive benefits.

Qualifications

• 3+ years recent industry experience in CPU and SoC clocking, reset, and power-management design.
• Expertise in CPU power state management and dynamic voltage/frequency scaling.
• Background in successful CPU or SoC development from architecture through tapeout.

Responsibilities

• Work with the architecture team to define power-management requirements.
• Design and implement core clocking and reset solutions.
• Collaborate with the physical implementation team to optimize designs.

Skills

CPU and SoC clocking

Reset control and design strategies

Power state definition and management

Dynamic voltage and frequency scaling (DVFS)

RTL design in Verilog, SystemVerilog, or VHDL

Attention to detail

Teamwork and communication skills

Object-oriented programming knowledge

Education

BS/MS degree in EE, CE, CS or related discipline

Tools

Spyglass

Git/GitHub

Jira

Confluence

Job description

About SiFive

SiFive is a leading company transforming computing with the open RISC‑V architecture, providing high‑performance, data‑intensive solutions across AI, machine learning, automotive, data center, mobile, and consumer markets.

Job Description

SiFive seeks a Power‑Management/Reset/Clock Micro‑Architect and RTL Design Engineer to design industry‑leading CPU and interconnect IP, enabling rapid adoption of RISC‑V across a broad range of verticals.

Responsibilities

• Work with the architecture team to understand and define power‑management requirements.
• Architect, design and implement core clocking, reset and power‑management solutions.
• Develop micro‑architecture specifications.
• Document knowledge and collaborate openly with team members.
• Perform initial sandbox verification and work with the design verification team to create and execute thorough verification test plans.
• Collaborate with the physical implementation team to optimize physical design for frequency, area and power goals.
• Partner with the software team to enable and optimize power‑management features.

Requirements

• 3+ years recent industry experience in CPU and SoC clocking, reset, and power‑management design.
• Experience in high‑performance, energy‑efficient CPU and SoC designs.
• Expertise in CPU and SoC clocking, reset, and power‑management, including:
• Reset control and design strategies: clock distribution, dynamic clocking, clock gating, and clock‑boundary crossing.
• Power state definition and management; Power Management Unit (PMU) design.
• Dynamic and static power‑reduction techniques, including retention and power‑up/down sequencing.
• Dynamic voltage and frequency scaling (DVFS) and DI/dT mitigation strategies.
• Understanding of DFT, MBIST, debug and error handling in CPU designs.
• Power‑aware simulation.
• Proficient in RTL design in Verilog, SystemVerilog, or VHDL.
• Strong grasp of RTL quality checks (Lint, CDC, RDC, etc.).
• Hands‑on experience with Spyglass is a plus.
• Attention to detail and focus on high‑quality design.
• Strong teamwork and communication skills.
• Knowledge of at least one object‑oriented and/or functional programming language.
• Background in successful CPU or SoC development from architecture through tapeout.
• BS/MS degree in EE, CE, CS or related discipline, or equivalent experience.

Nice to Have

• Experience with AMBA Interconnect Protocols (AXI, AHB, APB).
• Experience with AMBA Low Power Protocol Interface (P‑channel, Q‑channel).
• Experience with Scala/Chisel, Bluespec, or similar DSL for configurable hardware.
• Knowledge of RISC‑V architecture.
• Experience with Git/GitHub, Jira, Confluence.

Benefits

• Base pay range: $158,760.00 – $194,040.00 (varies by location).
• Eligible for variable/incentive compensation and/or equity.
• Comprehensive benefits: medical, vision, dental, 401(k) plan, employee stock option program.
• Flexible paid time off and other benefits.

Equal Opportunity

SiFive is proud to be an equal employment opportunity workplace.

SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.

All applicants will be required to complete a Form I‑9 and, if applicable, the E‑Verify process.