Power Management Engineer for High‑Performance RISC‑V SoCs

SiFive, Inc.; Santa Clara (CA); On-site; USD 206,000 - 251,000; Full time

Benefits offered by this job

Competitive compensation

401(k) plan

Employee stock option program

Job summary

SiFive is seeking a Power-Management/Reset/Clock Micro-Architect and RTL Design Engineer to pioneer PMU, clocking and power strategies for high-performance RISC-V CPU and SoC IP. You will work on highly-configurable hardware generators, collaborating with architecture, verification, and software teams to deliver fast, reliable hardware.

The role involves microarchitecture development, sandbox verification, and close coordination with physical design to hit frequency and power targets, enabling

Qualifications

• 5+ years of experience in CPU/SoC clocking, reset and power-management logic designs.
• Experience in high-performance, energy-efficient CPU/SoC designs.
• Strong knowledge of clocking, reset design, and PMU.
• Familiarity with DVFS and dynamic power management techniques.
• Experience with RTL quality checks (Lint, CDC, RDC).

Responsibilities

• Define power management requirements with the architecture team.
• Architect, design and implement core clocking, reset and power management solutions.
• Develop microarchitecture specifications and ensure documentation.
• Collaborate across verification, physical design, and software teams to optimize PM features.
• Participate in sandbox verification and verification test planning.
• Support physical implementation to meet frequency, area and power goals.

Skills

Verilog/SystemVerilog

RTL design

Power management

DVFS

AMBA AXI/AMBA

C/C++

Education

BS/MS in EE/CS or related

Tools

Spyglass

VHDL

Git/Jira/Confluence

Job description

SiFive is seeking a Power-Management/Reset/Clock Micro-Architect and RTL Design Engineer to pioneer PMU, clocking and power strategies for high-performance RISC-V CPU and SoC IP. You will work on highly-configurable hardware generators, collaborating with architecture, verification, and software teams to deliver fast, reliable hardware.

The role involves microarchitecture development, sandbox verification, and close coordination with physical design to hit frequency and power targets, enabling