RISC-V Power Management Engineer — High-Perf SoC

SiFive; Boston (MA); On-site; USD 206,000 - 251,000; Full time

Benefits offered by this job

Healthcare

401(k) plan

Stock option program

Job summary

SiFive is seeking a Power-Management/Reset/Clock Micro-Architect and RTL Design Engineer to design industry-leading CPU cores and interconnect IP based on RISC-V. You will create PM, reset, and clocking solutions forming the central nervous system for cutting-edge CPU and SoC IP designs.

Join a fast-paced team delivering hardware at the speed of software. The role involves microarchitecture development, verification, and collaboration with architecture, physical design, and software teams to

Qualifications

• 3+ years in CPU/SoC clocking, reset and power-management logic.
• Experience in high-performance, energy-efficient CPU/SoC designs.
• Proficiency with RTL design in Verilog/SystemVerilog or VHDL.

Responsibilities

• Define power management requirements with the architecture team.
• Architect and implement core clocking, reset and PM solutions.
• Develop microarchitectures and document designs for team collaboration.
• Perform sandbox verification and support full verification plans.
• Collaborate with physical design to meet frequency, area and power goals.
• Coordinate with software to enable PM features.

Skills

Power management

Reset design

Clocking design

Verilog/SystemVerilog

VHDL

DVFS

RTL quality checks

OO language

Education

BS/MS EE/CE/CS

Tools

Spyglass

Verilog toolchains

Job description

SiFive is seeking a Power-Management/Reset/Clock Micro-Architect and RTL Design Engineer to design industry-leading CPU cores and interconnect IP based on RISC-V. You will create PM, reset, and clocking solutions forming the central nervous system for cutting-edge CPU and SoC IP designs.

Join a fast-paced team delivering hardware at the speed of software. The role involves microarchitecture development, verification, and collaboration with architecture, physical design, and software teams to