Principal Custom Circuit Designer - High-Performance

Velaura; Santa Clara (CA); On-site; USD 125,000 - 500,000; Full time

Benefits offered by this job

Equity participation

Job summary

Velaura seeks a Sr. Staff/Principal Custom Circuit Design Engineer to lead architecture, design, and optimization of high-performance, low-power standard cells and custom digital circuits for AI and HPC silicon.

You will drive transistor-level innovation across FinFET/GAA nodes, mentor engineers, and collaborate with layout, CAD, and product teams to deliver robust PPA and manufacturability.

Qualifications

• 10+ years of experience in custom digital circuit design, standard cell development, or memory circuit design.
• Strong expertise in transistor-level CMOS circuit design for advanced technology nodes.
• Proven experience designing and optimizing high-performance, low-power standard cell libraries.
• Deep understanding of advanced process technologies including FinFET and GAA.
• Extensive experience with circuit simulation tools such as HSPICE, PrimeSimXA, or Spectre.

Responsibilities

• Lead the architecture, design, and optimization of high-performance, low-power standard cells for advanced process technologies.
• Design and optimize transistor-level circuits including latches, flip-flops, multiplexers, AOI/OAI, XOR/XNOR, encoders, decoders, level shifters, and arithmetic cells.
• Architect and develop advanced arithmetic building blocks, including adders, multipliers, MAC units.
• Develop schematics using Cadence Virtuoso and perform post-layout validation via parasitic extraction.
• Perform circuit verification across PVT corners using HSPICE, PrimeSim XA, or Spectre.

Skills

CMOS circuit design

Standard cell development

Transistor-level design

FinFET/GAA knowledge

Circuit simulation (HSPICE/PrimeSim/Sp

Education

Master's or Ph.D. in Electrical Engineering

Tools

Cadence Virtuoso

StarRC

Quantus

HSPICE

PrimeSim XA

Spectre

Liberate/PrimeLib

Job description

Velaura seeks a Sr. Staff/Principal Custom Circuit Design Engineer to lead architecture, design, and optimization of high-performance, low-power standard cells and custom digital circuits for AI and HPC silicon.

You will drive transistor-level innovation across FinFET/GAA nodes, mentor engineers, and collaborate with layout, CAD, and product teams to deliver robust PPA and manufacturability.