Senior ASIC Validation Engineer – Post-Silicon Chiplet/UCIe

Eridu; San Francisco (CA); On-site; USD 140,000 - 230,000; Full time

Job summary

Eridu, a Silicon Valley hardware startup, is hiring a Post-Silicon ASIC Validation Engineer to lead bring-up and validation of multi-die networking SoCs and chiplet platforms. You will own validation planning, define coverage, and drive test execution across high-speed interconnects like UCIe, SerDes, PCIe, and Ethernet PHYs in collaboration with architecture, design, firmware, and system teams.

This role offers opportunities to shape next-generation networking SoCs, develop automation, and

Qualifications

• Experience in post-silicon validation and bring-up of complex ASICs or SoCs.
• Hands-on experience with UCIe, PCIe and high-speed interconnects.
• Proficiency in Python for scripting, automation, and data analysis.

Responsibilities

• Drive post-silicon validation and bring-up of networking ASICs and chiplet-based SoCs.
• Own validation planning, coverage definition, and test execution across UCIe, SerDes, and networking subsystems.
• Develop automation and test infrastructure for high-speed link and protocol validation (Python).
• Perform silicon bring-up, including power sequencing, link training, and PHY initialization.
• Execute link-level and system-level validation of UCIe interfaces, die-to-die interconnects, and high-bandwidth chiplet fabrics.
• Debug complex cross-domain issues spanning RTL, firmware, analog PHY, and package-level interactions.
• Characterize signal integrity, latency, throughput, and thermal/power behavior across PVT corners.
• Collaborate with board design and test engineering teams on validation platforms, sockets, and characterization boards.

Skills

Post-silicon validation

UCIe/SoC interconnects

Python scripting

Team collaboration

Signal integrity understanding

Education

B.S./M.S. in Electrical Engineering or Computer Engineering

Tools

Oscilloscopes

Logic analyzers

JTAG debuggers

BERTs

Job description

Eridu, a Silicon Valley hardware startup, is hiring a Post-Silicon ASIC Validation Engineer to lead bring-up and validation of multi-die networking SoCs and chiplet platforms. You will own validation planning, define coverage, and drive test execution across high-speed interconnects like UCIe, SerDes, PCIe, and Ethernet PHYs in collaboration with architecture, design, firmware, and system teams.

This role offers opportunities to shape next-generation networking SoCs, develop automation, and