Lead Post-Silicon Validation Engineer, UCIe

Synopsys, Inc.; Hillsboro (OR); Hybrid; USD 140,000 - 170,000; Full time

Job summary

Synopsys, Inc. seeks an experienced engineer to lead post-silicon validation of UCIe die-to-die IP, guiding test plans, silicon sign-off, and result interpretation. You will build automation in Python and C/C++, mentor teammates, and work with customers during bring-up and debugging to ensure robust silicon performance.

Ideal candidates have deep expertise in high-speed interfaces, UCIe, and lab instrumentation, delivering clear, actionable data for AI and data-center silicon projects.

Qualifications

• Bachelor's degree in Electrical Engineering or Computer Engineering with 8+ years of related experience, or a Master's with 6+ years.
• Extensive hands-on post-silicon validation, high-speed mixed-signal interfaces, and debug, with UCIe experience preferred.
• Strong software development skills in Python, C, and C++, with solid software engineering practices.

Responsibilities

• Own post-silicon validation and characterization strategy for UCIe die-to-die IP from test plan to silicon sign-off.
• Architect and develop lab automation software for data capture, test execution, and result processing in Python/C/C++.
• Lead complex debug across circuit design, packaging, and protocol layers to root-cause failures.
• Support customers with bring-up and debug of silicon via on-site visits and remote sessions.
• Develop characterization methodologies for die-to-die links using on-die instrumentation and bench equipment.

Skills

Post-silicon validation

UCIe die-to-die interface

Python

C/C++

GitLab/Jira/Confluence

Education

BSc or MSc in Electrical/Computer Engineering

Tools

GitLab

Jira

Confluence

Job description

Synopsys, Inc. seeks an experienced engineer to lead post-silicon validation of UCIe die-to-die IP, guiding test plans, silicon sign-off, and result interpretation. You will build automation in Python and C/C++, mentor teammates, and work with customers during bring-up and debugging to ensure robust silicon performance.

Ideal candidates have deep expertise in high-speed interfaces, UCIe, and lab instrumentation, delivering clear, actionable data for AI and data-center silicon projects.