Hybrid ASIC Verification Intern

Hewlett Packard Enterprise Company; Roseville (CA); Hybrid; USD 48,000 - 56,000; Part time

Job summary

Hewlett Packard Enterprise Company in Roseville, CA is seeking an ASIC Post-Si Verification Engineering Intern. The role supports RTL/Physical Design, Pre-/Post-Silicon verification, and tool development within the ASIC/VLSI team.

You will learn from senior engineers and contribute to multiple assignments based on your skills. The position is designed for students pursuing a Bachelor’s or Master’s in a technical field, with at least 3 years of engineering coursework completed, and a strong

Qualifications

• Currently pursuing a Bachelor's or Master's degree in Computer Engineering, Computer Science, Electrical Engineering or a related technical field.
• At least 3rd Year of engineering courses completed.

Responsibilities

• Assist with RTL/Physical Design and Pre-Silicon verification.
• Support Post-Silicon verification and Formal Verification activities.
• Contribute to Script or Tool development and schedule breakdowns.
• Document generation and other duties based on student skills and business needs.

Skills

Verilog

SystemVerilog

Python

PERL

TCL

C

C++

Teamwork

Problem solving

Communication

Education

Bachelor's or Master's in Computer Engineering/CS/EE

At least 3rd Year of engineering courses

Job description

Hewlett Packard Enterprise Company in Roseville, CA is seeking an ASIC Post-Si Verification Engineering Intern. The role supports RTL/Physical Design, Pre-/Post-Silicon verification, and tool development within the ASIC/VLSI team.

You will learn from senior engineers and contribute to multiple assignments based on your skills. The position is designed for students pursuing a Bachelor’s or Master’s in a technical field, with at least 3 years of engineering coursework completed, and a strong