Physical Design Engineer (PnR / PPA / Timing Closure) - Austin TX

She Jobs; Austin (TX); On-site; USD 120,000 - 180,000; Full time

Job summary

She Jobs is seeking a Physical Design Engineer to lead block-level PD from netlist to GDSII in an advanced node environment. The role emphasizes PPA optimization, timing convergence, and close collaboration with RTL/DFT/STA teams to ensure successful tapeouts.

Qualifications include strong experience in Physical Design and PnR, floorplanning, CTS, routing, and STA, with proficiency in industry tools and EMIR analysis. Bachelor’s or Master’s in Electrical/Electronics Engineering preferred.

Qualifications

• Experience in Physical Design and PnR flow.
• Hands-on experience with floorplanning, placement, CTS, routing, and signoff.
• Experience optimizing Power, Performance, and Area (PPA).
• Ability to achieve timing closure across corners and modes.
• Identify and resolve timing, std cell, and EM/IR violations.

Responsibilities

• Drive block-level physical design implementation from netlist to GDSII.
• Perform floorplanning, power planning, placement, CTS, routing, and physical verification.
• Optimize designs for PPA targets.
• Achieve timing closure across multiple corners and modes.
• Analyze and resolve setup, hold, transition, capacitance, and noise violations.
• Develop timing constraints (SDC) and STA signoff methodologies.
• Perform EMIR analysis and closure.
• Collaborate with RTL, DFT, STA, and Signoff teams for tapeout.
• Debug physical design issues and drive convergence within schedules.

Skills

Physical design

PnR flow

Timing convergence

Problem solving

Cross-functional teamwork

Education

Bachelor's or Master's degree in Electrical/Electronics Engineering

Tools

Synopsys Fusion Compiler/ICC2

PrimeTime

Cadence Innovus

RedHawk

Voltus

Job description

Job Description

We are looking for a Physical Design Engineer with strong expertise in Place & Route (PnR), Power-Performance-Area (PPA) optimization, and timing convergence for advanced technology nodes.

Key Responsibilities

• Drive block-level physical design implementation from netlist to GDSII.
• Perform floorplanning, power planning, placement, clock tree synthesis (CTS), routing, and physical verification.
• Optimize designs for Power, Performance, and Area (PPA) targets.
• Achieve timing closure across multiple corners and modes.
• Analyze and resolve setup, hold, transition, capacitance, and noise violations.
• Develop and maintain timing constraints (SDC) and STA signoff methodologies.
• Perform EMIR (Electromigration & IR Drop) analysis and closure.
• Collaborate with RTL, DFT, STA, and Signoff teams to ensure successful tapeout.
• Debug physical design issues and drive design convergence within project schedules.

Required Skills

Strong experience in Physical Design and PnR flow.

Hands-on expertise in:

• Floorplanning
• Placement & Optimization
• Clock Tree Synthesis (CTS)
• Routing
• Timing Closure
• Static Timing Analysis (STA)
• Timing Constraints (SDC)
• EMIR Analysis
• PPA Optimization

Experience with industry-standard EDA tools such as:

• Synopsys Fusion Compiler / ICC2
• PrimeTime
• Cadence Innovus (optional)
• RedHawk / Voltus (EMIR)

Good understanding of low-power design techniques and signoff methodologies.

Preferred Qualifications

• Bachelor's or Master's degree in Electrical/Electronics Engineering.
• Experience in advanced nodes (7nm/5nm/3nm preferred).
• Strong debugging and problem-solving skills.
• Experience working with cross-functional silicon teams.