Physical Design Engineer

Amiseq Inc.; United States; On-site; USD 110,000 - 165,000; Full time

Job summary

Amiseq Inc. is seeking a highly skilled Physical Design Engineer to drive block-level implementation for advanced ASIC/SoC designs, focusing on floorplanning, placement, CTS, routing, and ECO tasks.

You will optimize timing, power, and area, support signoff, and collaborate with STA, DFT, and RTL teams. Proficiency in TCL/Perl/Python and experience with LEF/DEF, Liberty, and Verilog are essential.

Qualifications

• Strong ASIC physical design and implementation flow.
• Hands-on experience with Fusion Compiler and full-chip flows.
• Experience in floorplanning, placement, CTS, routing, and ECO implementation.
• Knowledge of timing analysis and timing closure methods.
• Understanding of congestion management and utilization optimization.
• Familiarity with LEF/DEF, Liberty, Verilog formats; IR Drop, EM, and PV basics.
• Strong TCL, Perl, or Python scripting skills; excellent debugging and teamwork.

Responsibilities

• Execute block-level physical design implementation from floorplan to tape-out.
• Develop and optimize floorplans, macro placement, and power-aware design methodologies.
• Perform placement optimization to achieve timing, power, area, and congestion targets.
• Drive Clock Tree Synthesis (CTS), routing, and ECO implementation activities.
• Support timing analysis, timing closure, and signoff readiness.
• Optimize design utilization, congestion, and routability across implementation stages.
• Perform DFM-related fixes and support signoff closure requirements.
• Collaborate with STA, DFT, and RTL teams to resolve implementation issues.
• Support tape-out activities and ensure design quality requirements are met.
• Develop automation scripts using TCL, Perl, and Python to improve design productivity.

Skills

ASIC physical design

Floorplanning

Placement

CTS

Routing

ECO implementation

Timing analysis

Timing closure

Congestion management

Utilization optimization

LEF/DEF

Liberty

Verilog

IR Drop

EM analysis

Physical Verification

TCL scripting

Perl scripting

Python scripting

Debugging

Problem-solving

Teamwork

Tools

Synopsys Fusion Compiler

Job description

We are seeking a highly skilled Physical Design Engineer to drive block-level implementation and optimization activities for advanced ASIC/SoC designs. The ideal candidate will have strong expertise in physical design flow, timing, power, area optimization, and tape-out support.

Key Responsibilities:

• Execute block-level physical design implementation from floorplan to tape-out.
• Develop and optimize floorplans, macro placement, and power-aware design methodologies.
• Perform placement optimization to achieve timing, power, area, and congestion targets.
• Drive Clock Tree Synthesis (CTS), routing, and ECO implementation activities.
• Support timing analysis, timing closure, and signoff readiness.
• Optimize design utilization, congestion, and routability across implementation stages.
• Perform DFM-related fixes and support signoff closure requirements.
• Collaborate with STA, DFT, and RTL teams to resolve implementation issues.
• Support tape-out activities and ensure design quality requirements are met.
• Develop automation scripts using TCL, Perl, and Python to improve design productivity.

Required Qualifications:

• Strong understanding of ASIC physical design and implementation flow.
• Hands-on experience with Synopsys Fusion Compiler.
• Experience in floorplanning, placement, CTS, routing, and ECO implementation.
• Knowledge of timing analysis fundamentals and timing closure methodologies.
• Understanding of congestion management, utilization optimization, and routing concepts.
• Familiarity with LEF/DEF, Liberty, Verilog, and standard physical design file formats.
• Basic understanding of IR Drop, EM analysis, and Physical Verification flows.
• Strong scripting skills in TCL, Perl, and/or Python.
• Excellent debugging, problem-solving, and teamwork skills.

Preferred Qualifications:

• Experience with advanced technology nodes and full-chip implementation.
• Exposure to signoff tools, DFM methodologies, and successful tape-out cycles.