Physical Design Intern: End-to-End Silicon Flow (Onsite)

Wayne State University; Santa Clara (CA); On-site; USD 68,880 - 96,432; Full time

Benefits offered by this job

Highly competitive compensation package

Benefits

Equal opportunity employer

Job summary

A leading AI technology firm is hiring a Physical Design Intern for its Santa Clara office. This hands-on role involves working from synthesis through tapeout alongside experienced engineers to optimize advanced silicon designs. The ideal candidate is pursuing a degree in Electrical Engineering or similar, with a solid grasp of logic design and scripting skills. Competitive hourly compensation ranges from $50 to $70 based on experience and skills.

Qualifications

• Currently pursuing a degree in Electrical Engineering, Electrical and Computer Engineering, Computer Engineering, or Computer Science.
• Solid understanding of logic design and transistor-level concepts.
• Familiarity with physical design tools and techniques.

Responsibilities

• Analyze and improve design metrics including Power, Performance, and Area (PPA).
• Collaborate with teams to influence early design decisions.
• Explore and implement new design flows and tools for optimization.

Skills

Logic design

VLSI design

Transistor-level concepts

PnR tools

Timing analysis

Power optimization techniques

Scripting in Tcl

Scripting in Perl

Scripting in Shell

Scripting in Python

Education

Currently pursuing a BS, MS, or PhD in EE, ECE, CE, or CS

Job description

A leading AI technology firm is hiring a Physical Design Intern for its Santa Clara office. This hands-on role involves working from synthesis through tapeout alongside experienced engineers to optimize advanced silicon designs. The ideal candidate is pursuing a degree in Electrical Engineering or similar, with a solid grasp of logic design and scripting skills. Competitive hourly compensation ranges from $50 to $70 based on experience and skills.