AI-Driven Physical Design & Timing Intern

NVIDIA Corporation; Santa Clara (CA); Hybrid; USD 28,000 - 98,000; Full time

Benefits offered by this job

Intern benefits

Job summary

NVIDIA Corporation is seeking a motivated Physical Design and Timing Engineer Intern for Summer 2027 in Santa Clara. You will drive physical design, power, and timing closure for high-frequency designs and assist from RTL to GDSII. The role emphasizes AI/ML techniques to accelerate workflows and requires strong STA and EDA tool familiarity.

Applicants should be pursuing an MS or Ph.D. in Electrical or Computer Engineering, with programming skills in Python, Perl/Tcl, and exposure to Cadence,

Qualifications

• Pursuing an MS or Ph.D. in Electrical or Computer Engineering.
• Familiarity with applying AI/ML techniques to physical design workflows.
• Knowledge of STA, power analysis, and power reduction; experience with EDA tools.

Responsibilities

• Drive physical design, power, and timing closure for high-frequency designs.
• Contribute to frontend and backend implementation from RTL to GDSII.
• Run physical design experiments and help develop flows and methodologies.

Skills

STA knowledge

Power analysis

Python

Perl/Tcl

EDA tools

AI/ML for EDA

Placement/Routing

Clock tree

Education

MS or Ph.D. in Electrical or Computer Engineering

Tools

Cadence

Synopsys

Siemens

Job description

NVIDIA Corporation is seeking a motivated Physical Design and Timing Engineer Intern for Summer 2027 in Santa Clara. You will drive physical design, power, and timing closure for high-frequency designs and assist from RTL to GDSII. The role emphasizes AI/ML techniques to accelerate workflows and requires strong STA and EDA tool familiarity.

Applicants should be pursuing an MS or Ph.D. in Electrical or Computer Engineering, with programming skills in Python, Perl/Tcl, and exposure to Cadence,