Physical Design Engineer

Acceler8 Talent; Mountain View (CA); On-site; USD 180,000 - 280,000; Full time

Job summary

Acceler8 Talent is seeking a senior physical-design engineer to own blocks of a next‑gen AI accelerator from floorplanning through sign‑off. You will drive timing, power, area, and verification requirements with architects and RTL teams, while coordinating with foundries, EDA vendors and packaging partners to ensure timely tape-out.

The role targets 7nm or below with hands‑on experience in full-flow PD, using Cadence Innovus, Fusion Compiler, and PrimeTime/Tempus for sign-off.

Qualifications

• 8+ years of hands-on physical-design experience.
• Experience with high-performance designs at 7nm or below.
• Full-flow ownership from synthesis and floorplanning through sign-off.
• Hands-on timing sign-off experience using PrimeTime, Tempus, or equivalent.
• Experience working closely with architecture, RTL, foundry, and EDA teams.
• Track record of taking complex silicon through tape-out.

Responsibilities

• Own physical design for one or more blocks of a new AI accelerator from floorplanning through sign-off.
• Close timing, power, area, congestion, and physical-verification requirements.
• Develop AI-assisted flows to accelerate physical-design and sign-off timelines.
• Collaborate with architects and RTL designers to resolve implementation trade-offs.
• Work with EDA vendors, foundries, packaging, and verification teams.
• Deliver complex blocks through tape-out and first silicon.

Skills

Physical design

Floorplanning

Synthesis

Placement

Routing

Timing closure

Power/area/congestion

Tools

Cadence Innovus

Synopsys Fusion Compiler

PrimeTime

Tempus

Job description

I’m working with an AI compute startup rebuilding the hardware and software stack around extreme compute density.

The team is developing a tightly integrated platform spanning advanced silicon, packaging, firmware, compilers, kernels, and infrastructure. This is broader than a conventional accelerator project, with physical-design decisions directly affecting the architecture and performance of the complete system.

This role will own physical design for one or more blocks of a new AI accelerator, from initial floorplanning through final sign-off.

You’ll work on problems such as:

• Owning synthesis, floorplanning, placement, routing, CTS, and sign-off
• Closing timing, power, area, congestion, and physical-verification requirements
• Developing AI-assisted flows to accelerate physical-design and sign-off timelines
• Working with architects and RTL designers to resolve implementation trade-offs
• Collaborating with EDA vendors, foundries, packaging, and verification teams
• Delivering complex blocks through tape-out and first silicon.

Looking for engineers who have:

• 8+ years of hands-on physical-design experience
• Experience with high-performance designs at 7nm or below
• Full-flow ownership from synthesis and floorplanning through sign-off
• Strong experience with Cadence Innovus, Synopsys Fusion Compiler, or equivalent
• Hands-on timing sign-off experience using PrimeTime, Tempus, or equivalent
• Experience working closely with architecture, RTL, foundry, and EDA teams
• A track record of taking complex silicon through tape-out.

Nice to have:

• CoWoS, chiplet, 2.5D, or 3D packaging experience
• Thermal, IR-drop, electromigration, or signal-integrity sign-off
• Experience with AI accelerators, CPUs, GPUs, or other high-performance compute silicon
• Experience building or improving physical-design automation.

This is an opportunity to own foundational implementation decisions for a new AI computing platform alongside engineers with experience across advanced CPUs, custom AI silicon, and wafer-scale systems.