AI-Powered Physical Design & Timing Intern

NVIDIA Corporation; Santa Clara (CA); On-site; USD 28,000 - 98,000; Part time

Benefits offered by this job

Intern benefits

Job summary

NVIDIA invites motivated students to join our Physical Design and Timing Engineer – Intern team in Santa Clara, CA. You will contribute to high‑frequency, low‑power design, and assist both frontend and backend flows from RTL to GDSII, with emphasis on AI/ML‑driven design automation.

The internship emphasizes hands‑on flow development, STA and power reduction tasks, and exposure to industry‑standard EDA tools.

Qualifications

• Pursuing an MS or Ph.D. in Electrical or Computer Engineering.

Responsibilities

• Drive physical design, power, and timing closure for high-frequency and low-power designs.
• Help drive frontend and backend implementation in select areas, from RTL to GDSII.
• Run physical design experiments and help develop flows and methodologies.

Skills

AI/ML techniques

STA

Power analysis

Logic synthesis

Physical optimization

EDA tools

Perl

Python

Tcl

Make

Education

MS or Ph.D. in Electrical or Computer Engineering

Tools

Cadence

Synopsys

Siemens

Job description

NVIDIA invites motivated students to join our Physical Design and Timing Engineer – Intern team in Santa Clara, CA. You will contribute to high‑frequency, low‑power design, and assist both frontend and backend flows from RTL to GDSII, with emphasis on AI/ML‑driven design automation.

The internship emphasizes hands‑on flow development, STA and power reduction tasks, and exposure to industry‑standard EDA tools.