Lead ASIC Physical Design Engineer

Socket.dev; San Diego (CA); On-site; USD 123,000 - 250,000; Full time

Job summary

Qualcomm Technologies, Inc. is seeking highly motivated Physical Design Engineers across multiple career levels to join its ASIC implementation team in San Diego and other locations.

You will contribute to physical design, floorplanning, CTS, timing closure, and signoff from synthesis to tapeout, collaborating with architecture, RTL, CAD, and product engineering teams. The role emphasizes low-power techniques, automation, and design optimization, with opportunities from Engineer to Principal

Qualifications

• Bachelor’s degree and 4+ years of ASIC design/verification experience.
• Master’s degree and 3+ years of ASIC design/verification experience.
• PhD and 2+ years of ASIC design/verification experience.

Responsibilities

• Support implementation and physical design closure of ASIC and SoC blocks.
• Execute floorplanning, placement, CTS, routing, timing analysis, and physical verification tasks.
• Assist in identifying and resolving timing, congestion, power, and physical implementation challenges.
• Develop scripts and automation solutions to improve design productivity.
• Collaborate with cross-functional teams to support successful project execution.
• Drive timing closure and power optimization across multiple modes and corners.

Skills

ASIC design

Verification

Python scripting

Linux/Unix

Team collaboration

Education

Bachelor’s degree in Science, Engineering, or related field

Master’s degree in Science, Engineering, or related field

PhD in Science, Engineering, or related field

Tools

Cadence Innovus

Synopsys Fusion Compiler

Synopsys PrimeTime

Job description

Qualcomm Technologies, Inc. is seeking highly motivated Physical Design Engineers across multiple career levels to join its ASIC implementation team in San Diego and other locations.

You will contribute to physical design, floorplanning, CTS, timing closure, and signoff from synthesis to tapeout, collaborating with architecture, RTL, CAD, and product engineering teams. The role emphasizes low-power techniques, automation, and design optimization, with opportunities from Engineer to Principal